SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 21

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
exclusive-or, complement and rotate (right, left, or nib-
ble swap).
The register ACC is the accumulator, the register B is
dedicated during multiply and divide and serves as
both source and destination. During all other opera-
tions the register B is simply another location of the
special function register space and may be used for
any purpose.
2.2.8.1.5. Boolean Processor
The Boolean processor is an integral part of the micro-
controller architecture. It is an independent bit proces-
sor with its own instruction set, its own accumulator
(the carry flag) and its own bit-addressable RAM and I/
O. The bit manipulation instructions allow the direct
addressing of 128 bits within the internal data RAM
and several bits within the special function registers.
The special function registers which have addresses
exactly divisible by eight contain directly addressable
bits.
The Boolean processor can perform, on any address-
able bit, the bit operations of “set”, “clear”, “comple-
ment”, “jump-if-set”, “jump-if-not-set”, “jump-if-set then-
clear” and “move to/from carry”. Between any address-
able bit (or its complement) and the carry flag it can
perform the bit operation of logical AND or logical OR
with the result returned to the carry flag.
2.2.8.1.6. Program Status Word Register (PSW)
The PSW flag bits record microcontroller status infor-
mation and control the operation of the microcontroller.
The carry (CY), auxiliary carry (AC), two user flags (F0
and F1), register bank select (RS0 and RS1), overflow
(OV) and parity (P) flags reside in the program status
word register. These flags are bit-memory-mapped
within the Byte-memory-mapped PSW. The CY, AC,
Table 2–7: Related register
Micronas
Register Name
PSW
See Section 3. on page 110 for detailed register description.
7
CY
6
AC
5
F0
Sept. 10, 2004; 6251-556-3DS
4
and OV flags generally reflect the status of the latest
arithmetic operations. The CY flag is also the Boolean
accumulator for bit operations. The P-flag always
reflects the parity of the register ACC. F0 and F1 are
general purpose flags which are pushed onto the stack
as part of a PSW save (see Table 2–7).
The two register bank select bits (RS1 and RS0) deter-
mine which one of the four register banks is selected
as show in Table 2–6.
See Section 3. on page 110 for detailed register
description.
2.2.8.1.7. Stack Pointer (SP)
The 8-bit stack pointer contains the address at which
the last Byte was pushed onto the stack. This is also
the address of the next Byte that will be popped. The
SP is incremented during a push. SP can be read or
written to under software control. The stack may be
located anywhere within the internal data RAM
address space and may be as large as 256 Bytes.
Note: For memory above 64k, the memory extension
Table 2–6: Register banks
RS1
0
0
1
1
Bit Name
RS[1:0]
stack is used, refer to Section 2.5.3. on page 49.
3
RS0
0
1
0
1
Register Bank
0
1
2
3
2
OV
1
F1
Register Location
00
08
10
18
SDA 55xx
H
H
H
H
… 07
… 0F
… 17
… 1F
H
H
H
H
0
P
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