SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 13

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.1.3. Pixel Clock
The second clock system is the pixel clock (f
is programmable in a range from 10 … 32 MHz. It
serves the output part of the display FIFO and the D/A
converters. The pixel clock is derived from the high fre-
quent output of the PLL and line by line phase shifted
to the positive edge of the horizontal sync signal (nor-
mal polarity). Because the final display clock is derived
from a DTO (digital time oscillator) it has no equidistant
clock periods although the average frequency is exact.
This pixel clock generation system has several advan-
tages:
– The frequency of the pixel clock can be pro-
– Because the input of the PLL is already a signal with
– The resulting pixel clock follows the edge of the H-
2.1.4. Related Registers
Table 2–1: Related registers and bits
Micronas
Register Name
PCLK1
PCLK0
PCON
PSAVEX
See Section 3. on page 110 for detailed register description.
grammed independently from the horizontal line
period.
a relative high frequency, the resulting pixel fre-
quency has an extremely low jitter.
sync impulse without any delay and has always the
same quality than the sync timing of the deflection
controller.
Bit Name
7
PF[7:0]
SMOD
6
PDS
PIX
5
IDLS
Sept. 10, 2004; 6251-556-3DS
), which
4
SD
3
GF1
2
PF[10:8]
GF0
CLK_src
1
PDE
PLL_res
SDA 55xx
0
IDLE
PLLS
13