SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 14

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.2. Slicer and Data Acquisition
2.2.1. General Function
TVTPro provides a full digital data slicer including digi-
tal H- and V-sync separation and digital sync process-
ing. The acquisition interface is capable to process all
known data services transmitted in the Vertical Blank-
ing Interval VBI of a CVBS signal (Teletext, VPS, CC,
G+, WSS). Four different framing codes (two of them
freely programmable for each field) are available for
each field. Digital signal processing algorithms are
applied to compensate various disturbing influences
as there are:
– Noise measurement and compensation.
– Attenuation measurement and compensation.
– Group delay measurement and compensation.
Note: TVTPro is optimized for precise data clock
The CVBS input contains an on chip clamping circuit.
The integrated A/D converter has a 7 bit resolution.
The sampling frequency is 33.33 MHz.
Fig. 2–2: Block Diagram of Digital Slicer and Acquisition Interface
14
recovery and error free reception of data. Thus,
the reception of data services is widely unaf-
fected by noise and the actual transmission
channel characteristics.
CVBS
Noise,
Attenuation,
Group-Delay
Compensation
Noise,
Attenuation,
Group-Delay
Measurement
Data Slicer
Separation
Data
D-PLL
Sept. 10, 2004; 6251-556-3DS
Acquisition Interface
Sync Separation
The sliced data are synchronized to the data clock fre-
quency given by the clock-run-in. The framing code will
define the start of the data stream. The resulting valid
data will be written to the VBI data buffer. After line 23
is received an interrupt will be issued to the microcon-
troller. The microcontroller starts processing the buff-
ered data. That means, a SW module will check the
data for errors and store them in an assigned memory
area.
To improve the data signal quality the slicer control
logic generates horizontal and vertical windows during
which the reception of the framing code is allowed.
The framing code can be programmed individually for
each line, so that in each line a different data service
can be received. For VPS and WSS the framing code
is hardwired. All following acquisition tasks are per-
formed by the internal controller, so in principal the
data of any data service can be acquired.
2.2.2. Slicer Architecture
The slicer consists of three main blocks:
– The slicer
– The H/V synchronization for the slicer
– The acquisition interface
Ser/Par
Converter
Separation
FC-Check
H/V-Sync
Timing
&
&
H-PLL
Address
Decoder
Parameter
Buffer
VS1_IR
HS1_IR
L23_IR
CC_IR
to
Memory
DATA SHEET
Micronas