SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 66

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.12. Sync System
2.12.1. General Description
The display sync system is completely independent
from the acquisition sync system (CVBS timing) and
can either work as a sync master or as a sync slave
system.
Talking about ‘H/V-Syncs’ in this chapter and in
Section 2.13. on page 69 always refers to display
related H/V Syncs and never to CVBS related sync
timing.
In sync slave mode TVTpro receives the synchroniza-
tion information from two independent pins which
deliver separate horizontal and vertical signals or a
sandcastle impulse from which the horizontal and ver-
tical sync signals are separated internally. Due to the
not line locked pixel clock generation it can process
any possible horizontal and vertical sync frequency.
In sync master mode TVTpro delivers separate hori-
zontal and vertical signals with the same flexibility in
the programming of these periods as in sync slave
mode.
Fig. 2–10: TVTPro’s Display Timing
66
t
t
H_clmp_e
(BHCR)
H_clmp_b
H-Sync
(EHCR)
EVCR
VLR
BVCR
H-Sync Delay
(SDH)
Vertical Blacklevel Clamping
Character Display Area
Variable count of character columns (33..64)
t
H-period
Border
Sept. 10, 2004; 6251-556-3DS
(HPR)
2.12.1.1. Screen Resolution
The number of displayable pixels on the screen is
defined by the pixel frequency (which is independent
from horizontal frequency), the line period and number
of lines within a field. The screen is divided in three dif-
ferent regions:
2.12.1.1.1. Blacklevel Clamping Area
During horizontal and vertical blacklevel clamping, the
black value (RGB = 000) is delivered on output side of
TVTPro. Inside this area the BLANK pin and COR pin
are set to the same values which are defined as trans-
parency for subCLUT0 (see also Section 2.13.7.5. on
page 88). This area is programmable in vertical direc-
tion (in terms of lines) and in horizontal direction in
terms of 33.33 MHz clock cycles.
2.12.1.1.2. Border Area
The size of this area is defined by the sync delay regis-
ters (SDH and SDV) and the size of the character dis-
play area. The color and transparency of this area is
defined by a color look up vector. See Section 2.13.7.
on page 79).
Variable
Height
(25 rows)
V-Sync
Delay
(SDV)
DATA SHEET
Micronas