SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 59

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.9. Pulse Width Modulation Unit
The Pulse Width Modulation unit consists of 6 chan-
nels with 8 bit resolution and 2 channels with 14 bit
resolution PWM channels. PWM channels are pro-
grammed via special function registers and each chan-
nel can be enabled and disabled individually.
2.9.1. Reset Values
All the PWM unit registers as there are: PWME,
PWCOMP8 0-5, PWCOMP14 0-1, PWMCOMPEXT14
0-1, PWML and PWMH by default are reset to 00
2.9.2. Input Clock
The input clock fpwm to the PWM unit PWMU is
derived from f
and in slowdown mode 8.33 MHz.
In normal mode f
mode it is directly fed to the PWMU. Therefore PWM
unit is counting at 16.5 MHz in normal mode and
8.25 MHz in slow down mode. If the PR bit
PCOMPEXT14 0 (bit 0) is set the then the counting
frequency is half of that.
In addition the PWM_direct bit makes it possible to run
the PWM counter at system frequency, ignoring the PR
bit and the built in divide by 2 prescaler.
To reduce noise radiation, the different PWM-channels
are not switched ’on’ simultaneously with the same
counter value. The channels are switching on with one
clock cycle delay to the next channel: Channel 0: 0
clock cycles delayed, Channel 1: 1 clock cycle
delayed, …, Channel 5: 5 clock cycles, …, PWM14_0:
6 clock cycles, PWM14_1: 7 clock cycles delayed.
2.9.3. Port Pins
Port 1 is a dual function port. Under normal mode it
works as standard Port 1, in the alternate function
mode it outputs the PWM channels.
P1.0 … P1.5 corresponds to the six 8 bit resolution
PWM channels PWM8_0 … PWM8_5. P1.6 and P1.7
corresponds to the two 14 bit resolution PWM chan-
nels PWM14_0 and PWM14_1. PWM channels can be
individually enabled by corresponding bits in the
PWME register provided the PWM_Tmr bit is not set
(timer mode start bit).
Micronas
sys
. f
sys
sys
is divided by 2 and in slow down
is 33.33 MHz in normal mode
Sept. 10, 2004; 6251-556-3DS
H
.
2.9.4. Functional Description
2.9.4.1. 8-bit PWM
The base frequency of a 8 bit resolution DA converter
channel is derived from the overflow of a six bit
counter.
On every counter overflow, the enabled PWM lines
would be set to 1. Except in the case it the compare
value is set to zero.
In case the comparator bits (7 … 2) are set to 1, the
high time of the base cycle is 63 clock cycles. In case
all the comparator bits (7 … 0) including the stretching
bits are set to 1, the high time of the full cycle (4 base
cycles) is 255 clock cycles.
The corresponding PWCOMP8x register determines
the duty cycle of the channel. If the counter value is
equal to or greater than the compare value then the
output channel is set to zero. The duty cycle can be
adjusted in steps of fpwm as mentioned in Table 2–36.
In order to achieve the same resolution as 8-bit
counter, the high time is stretched periodically by one
clock cycle. The stretching cycle is determined based
on the two least significant bits in the corresponding
PWCOMP8x register.
The relationship for the stretching cycle can be seen in
Table 2–35 and the example below.
Table 2–35: 8-bit PWM stretching cycle relationship
Fig. 2–8: 8-bit PWM and the Stretching Cycles
PWCOMP8X
Bit 1
Bit 0
Cycle 0
Cycle 1 Cycle 2
Cycle Stretched
1, 3
2
‘stretched‘
SDA 55xx
Cycle 3
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