SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 37

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.3. Interrupt
2.3.1. Interrupt System
External events and the real-time operation of on-chip
peripherals require CPU service asynchronous to the
execution of any particular section of code. To couple
the asynchronous activities of these functions to nor-
mal program execution, a sophisticated multiple-
source, four-priority-level, nested interrupt system is
provided.
2.3.2. Interrupt Sources
The TVT microcontroller core is capable of handling up
to 24 interrupt sources. In Type<Default ¶ Font> 17
interrupts are implemented. The rest are reserved for
future use. The microcontroller acknowledges interrupt
requests from these 17 sources. Two external sources
via the INT0 and INT1 pins and two additional external
interrupts INTX0 (P3.1) and INTX1 (P3.7) are pro-
vided. On-chip peripherals also use interrupts: one
from each of the two internal counters, one from the
analog digital converter and one from UART. In addi-
tion there are four Data Acquisition related interrupts,
two display related interrupts and one interrupt indicat-
.
Fig. 2–4: Interrupt Handling Overview
Micronas
Interrrupt Request
Interrrupt Request
Interrrupt Request
Interrrupt Request
IEN0.x
IEN2.x
IEN3.x
IEN1.x
Note: x = 0 to 5
IEN0.
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IP1.x
IP0.x
Sept. 10, 2004; 6251-556-3DS
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Lowest
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ing change of channel, two interrupts are generated by
the WDT and PWM overflow in timer mode.
Timer 0 and Timer 1 overflows are indicated by
TCON(TF0) and TCON.(TF1). Interrupts are gener-
ated following a rollover in their respective registers
(except in Mode 3 when TCON(TH0) controls the
Timer 1 interrupt).
The external interrupts INT0 and INT1 are either level
or edge triggered depending on bits in TCON and
IRCON. Other external interrupts are level sensitive
and active high. Any edge triggering will need to be
taken care of by individual peripherals.
INTX0 and INTX1 can be programed to be either neg-
ative or positive edge triggered.
The analog digital converter interrupt is generated on
completion of the analog digital conversion.
2.3.3. Overview
A simple overview of the interrupt handling is shown in
Fig. 2–4.
SDA 55xx
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