T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 112
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T-8110L
Manufacturer Part Number
T-8110L
Description
Manufacturer
AGERE [Agere Systems]
Datasheet
1.T-8110L.pdf
(164 pages)
- Current page: 112 of 164
- Download datasheet (3Mb)
Ambassador T8110L H.100/H.110 Switch
11 Test and Diagnostics
11.2 Diagnostic Circuit Operation
The T8110L internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions
include the following:
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112
DIAG0—3, observability of internal testpoints via FG(7:0), GP(7:0):
— Internal testpoints are brought to chip I/O at FG and GP signals. Refer to Table 89 on page 107 and Table 91
DIAG4—5, internal state counter diagnostic modes:
— Break counter carry chains—this is used in conjunction with monitoring of the state counter bits at FG and GP,
— Shorten frame operation—the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input.
DIAG6, forced RESET of analog APLL1 feedback dividers:
— The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be
DIAG7, reserved.
DIAG8, interrupt controller diagnostics:
— When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0]
DIAG9, interrupt controller deassertion delay:
— Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts.
DIAG10—11, sync-to-frame command delay:
— Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock com-
on page 109 for testpoint assignment.
and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]).
The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz.
This is used in conjunction with the state counter modulo function, which when properly programmed allows
the internal state counter to roll over coincident with the /FR_COMP frame center.
held in a reset state.
inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the
FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits
from each tier group. Please see Section 10.2 on page 103 for more details.
mands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK.
(continued)
Agere Systems Inc.
February 2004
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