T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 33

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
5 Operating Control and Status
5.1 Control Registers
5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register
The clock register access select register controls the selection between accessing the active vs. the inactive set of
T8110L clock registers. The T8110L contains two sets of clock registers, X and Y. The X and Y register sets are
comprised of the registers listed in Table 33 on page 45, Clock Input Control Register Map, and Table 46 on page
53, Clock Output Control Register Map. Only one set is used at a time. It is selected based on the clock fallback
setup. The clock register set that is currently in use is denoted as the active set; see Section 6.3 on page 57 for
more details.
Table 19. Clock Register Access Select Register
5.1.5 Phase Alignment Select Register
The phase alignment select register selects the phase alignment configuration. For more details, see Section
6.4.5.1 on page 62. The T8110L internally generates an 8 kHz frame reference. Shown below are three configura-
tions to control phase alignment between this internally generated frame reference and a selected incoming frame
reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]).
!
!
!
Table 20. Phase Alignment Select Register
5.1.6 Fallback Control Register
The fallback control register allows user control over the active and inactive clock register sets. For more details,
see Section 6.7.1 on page 64. Writes to the fallback control register trigger the corresponding action, and the set
bit(s) are automatically cleared. The four commands are shown below:
!
!
Address
0x00106 Clock Register Access
Address
0x00107 Phase Alignment Select
Disable alignment, no realignment of unaligned frames
Snap alignment, immediate realignment of unaligned frames
Slide alignment, gradual realignment of unaligned frames
GO_CLOCKS. At initialization, the clock register Y set is active, the X set is inactive, and access is enabled to
the X set. The GO_CLOCKS command transitions the Y set to inactive and the X set to active. This command
can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame refer-
ence (synchronized to frame).
CLEAR_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets
after a fallback event has occurred. This command can either be performed immediately upon issue or can wait
to be performed until the next 8 kHz frame reference (synchronized to frame).
Byte
Byte
Select
Name
Name
(continued)
Bit(s) Mnemonic
7:0
Bit(s) Mnemonic
7:0
(continued)
PAFSR
CSASR
0000 0000
0000 0001
0000 0010
0000 0000
0000 0001
Value
Value
Ambassador T8110L H.100/H.110 Switch
Phase alignment is disabled (default).
Enable snap alignment.
Enable slide alignment.
Access inactive clock registers (default).
Access active clock registers.
Function
Function
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