T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 67

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.7 Clock Circuit Operation—Fallback and Failsafe
6.7.1 Clock Fallback (continued)
6.7.1.1 Fallback Scenarios—Fixed vs. Rotating Secondary (continued)
Table 54. Clock Fallback State Description
* Fallback event; refer to Section 6.7.1.1 on page 64.
† Fixed, rotating secondary; refer to Section 6.7.1.2 on page 65.
TO_SECONDARY Y is the active clock register
Clock Fallback
TO_PRIMARY
SECONDARY
PRIMARY
INITIAL
State
Y is the active clock register
set. Default value provides
XTAL1-div-4 reference.
X is the active clock register
set and controls APLL1
REFCLK.
set and controls APLL1
REFCLK.
Fallback flag is asserted.
Y is the active clock register
set and controls APLL1
REFCLK.
X is the active clock register
set and controls APLL1
REFCLK.
Fallback flag is asserted.
(continued)
Description
TO_SECONDARY Fallback is enabled and fallback event*
TO_PRIMARY
SECONDARY
SECONDARY
PRIMARY
PRIMARY
PRIMARY
Exit To
Ambassador T8110L H.100/H.110 Switch
(continued)
User issues GO_CLOCKS command
(set register 0x00108 bit 0).
occurs.
User issues CLEAR_FALLBACK com-
mand (set register 0x00108 bit 1) and
fallback type = fixed secondary
User issues CLEAR_FALLBACK com-
mand (set register 0x00108 bit 1) and
fallback type = rotating secondary
Fallback is enabled and fallback event*
occurs.
User issues CLEAR_FALLBACK com-
mand (set register 0x00108 bit 1) and
fallback type = fixed secondary
User issues CLEAR_FALLBACK com-
mand (set register 0x00108 bit 1) and
fallback type = rotating secondary
Exit Condition
†
†
.
.
†
†
.
.
67