T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 59

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.4 Clock Circuit Operation—APLL1
6.4.1 Main Clock Selection, Bit Clock, and Frame (continued)
6.4.1.2 Frame Center Sampling
Frame center samples are used in order to phase-align the incoming frame reference to the internally generated
frame reference; see Section 6.4.5.1 on page 62. The incoming frame reference signal is sampled with a recov-
ered clock (output of the APLL1 feedback divider) to determine the frame center. Frame center sampling is only
relevant when the main clock selection is based on a paired bit clock/frame reference, as follows.
Table 52. Frame Center Sampling
/CT_FRAME_A
/CT_FRAME_B
Frame Signal
/FR_COMP
/FR_COMP
LREF[4]
LREF[5]
LREF[6]
LREF[7]
(continued)
SCLK or /SCLKx2 (SC-bus)
Corresponding Bit Clock
/C16± (H-MVIP)
or /C4 (MVIP)
or C2 (MVIP)
CT_C8_A
CT_C8_B
LREF[0]
LREF[1]
LREF[2]
LREF[3]
(continued)
Ambassador T8110L H.100/H.110 Switch
Recovered 4.096 MHz, falling edge.
Recovered 8.192 MHz, rising edge.
Recovered 8.192 MHz, rising edge.
Recovered 2.048 MHz, rising edge.
Recovered 2.048 MHz, rising edge.
Recovered 2.048 MHz, rising edge.
Recovered 2.048 MHz, rising edge.
Recovered 2.048 MHz, rising edge.
Sample Clock
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