T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 51

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.1 Clock Input Control Registers
6.1.10 DPLL2 Input Selector (continued)
6.1.10.1 DPLL2 Rate Register
The DPLL2 rate register controls the DPLL2 output frequency.
Table 43. DPLL2 Register
6.1.11 NETREF1 Registers
The NETREF1 input selector, NETREF1 divider, and NETREF1 LREF select registers control the signal paths
used to generate CT_NETREF1 (see Figure 6 on page 44).
Table 44. NETREF1 Registers
* Selection of which LREF is controlled at register 0x00212.
Address
0x0020E DPLL2 Input Selector
0x0020F DPLL2 Rate
Address
0x00210 NETREF1 Input
0x00212 NETREF1 LREF
0x00211
Byte
Byte
Selector
NETREF1 Divider
Select
Name
Name
(continued)
Bit(s) Mnemonic
7:4
3:0
7:0
7:0
Bit(s) Mnemonic
7:0
7:0
NR1DR
N1DSN
N1LSR
N1ISN
(continued)
D2RSR
D2ISR
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256},
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
Value
0000
0001
0000
0001
0010
0100
1000
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
Ambassador T8110L H.100/H.110 Switch
Value
Divider input = selector output (default).
Divider input = external input NR1_DIV_IN.
Oscillator/XTAL1-div-8, 2.048 MHz (default).
Oscillator/XTAL1, 16.384 MHz.
CT_NETREF2 input.
LREF input*.
Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.
respectively.
Select LREF0 (default).
Select LREF0.
Select LREF1.
Select LREF2.
Select LREF3.
Select LREF4.
Select LREF5.
Select LREF6.
Select LREF7.
Main selector (default).
Main divider.
Resource divider.
T8110L internally generated frame.
External input PRI_REF_IN.
DPLL2 output off (default).
DPLL2 output at 1.544 MHz.
DPLL2 output at 3.088 MHz.
DPLL2 output at 6.176 MHz.
DPLL2 output at 12.352 MHz.
Function
Function
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