R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 129

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.3.2
R e v 1 . 0 1
Response PID
Set the response PID for each pipe with the PID bit of the DCPCTR and PIPExCTR registers.
Based on the results of the transaction, the controller may trigger the PID bit to be written.
The controller will trigger a write event to the PID bit in the following cases.
(1) Response PID setting for Host Controller function
(2) Response PID setting for Peripheral Controller function
(1) H/W setting of Response PID when Host Controller function is selected
(2) H/W setting of Response PID when Peripheral Controller function is selected
O c t 1 7 , 2 0 0 8
The response PID specifies the transaction execution.
Use the SUREQ bit to perform the DCP setup transaction.
The response PID specifies the response to a transaction from the Host.
Regardless of the value set in the PID bit, an ACK is always sent as a response to a setup transaction and the
USB request is stored in corresponding registers.
(a) NAK Setting:
(b) BUF setting: the BUF cannot be written by the controller
(c) STALL setting:
(a) NAK setting: Pipe is in disabled status; transaction cannot be executed.
(b) BUF setting: transaction is executed according to the buffer memory status.
(c) STALL setting: Pipe is in the disabled status; transaction cannot be executed.
(a) NAK setting: Always sends a NAK response when a transaction is issued.
(b) BUF setting: Responds to the transaction in accordance with the buffer memory status.
(c) STALL setting: Always sends a STALL response when a transaction is issued.
(a) NAK setting:
(b) BUF setting: the BUF cannot be written by the controller
(c) STALL setting:
(i)
(ii)
(iii) When DCPCFG register SHTNAK bit is set to “1” and a short packet is received in the data stage of
(iv) When a short packet is received during a bulk transfer and PIPECFG register SHTNAK bit is set to
(v)
(i)
(ii)
(i)
(ii) In bulk transfers when PIPECFG register SHTNAK bit is set to “1” and short packet is received
(iii) In bulk transfers when SHTNAK bit is set to “1” and the transfaction counter is completed.
For OUT direction, when there is send data in the buffer memory, an OUT token is issued.
For IN direction, if there is empty space in the buffer memory and it is receive enabled, an IN token is
issued.
In the following conditions, the PID bit is set to NAK and token issuance is automatically stopped.
In the following conditions, the PID bit is set to STALL and token issuance is automatically stopped.
(i) When a maximum packet size over error is detected for a received data packet
(ii) When a control transfer sequence error is detected
When SETUP token is received normally (only DCP)
In transfer types other than isochronous, when a receive error, such as No Response, bit stuffing
error or CRC error, occurs 3 times consecutively in response to a transferred token
In an isochronous transfer, when a receive error, such as bit stuffing error or CRC error, occurs 3
times consecutively in response to a transferred token
a control read transfer
“1”
When a transaction counter is completed during a bulk transfer and PIPECFG register SHTNAK bit
is set to “1”
STALL is received in response to a sent token
Received packet exceeds maximum packet size
p a g e 1 2 9 o f 1 8 3