R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 146

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.6.2
3.6.2.1 Setup Stage
3.6.2.2 Data Stage
3.6.2.3 Status Stage
3.6.2.4 Control Transfer Automatic Response Function
R e v 1 . 0 1
Control Transfer with Peripheral Controller Function Selected
The controller always responds with an ACK when it receives a normal setup packet. The controller operations in the
setup stage are as follows.
Always set “VALID=0” in the response process to a control transfer. In the “VALID=1” state, “PID=BUF” will not be set
and the data stage cannot be completed.
The VALID bit function allows the controller to temporarily stop a request in-process when it receives a new USB
request during a control transfer, and respond to the newest request.
In addition, the controller automatically judges the direction bit (bmRequestType bit 8) and the request data length
(wLength) of the received USB request and determines whether it is a control read transfer, control write transfer or
no-data control transfer, and then handles the stage transition. If the sequence is incorrect, a sequence error for the
control transfer stage transition interrupt occurs and is notified to the software. For more information concerning the
controller stage management, refer to Figure 3.11.
Use the DCP for data transfers in response to receiving a USB request.
Before accessing the DCP buffer memory, set the access direction in the CFIFOSEL register ISEL bit. Also set the
transfer direction in the DCPCFG register DIR bit.
The first data packet in the data stage must transmit the data PID as DATA1. To execute the transaction, set the data
PID as DATA1 in the DCPCFG register SQSET bit and set the PID bit to BUF.
Data transfer completion is detected by the BRDY and BEMP interrupts.
Use the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers.
For control write transfers in Hi-Speed operation, a NYET handshake is sent in accordance with the buffer memory
status. For more details, see Chapter 3.6.1.4,
When the DCPCTR register PID bit status is “PID=BUF”, set the CCPL bit to “1” to complete the control transfer.
After the above settings, the controller automatically executes the status stage in accordance with the data transfer
direction fixed in the setup stage. The detailed process is as follows.
The controller automatically sends a response to a normal SET ADDRESS request. If one of the following errors
occurs, a response must be sent by software.
All requests other than the SET ADDRESS request must be responded to by software.
(1) When a new setup packet is received, the controller sets the following bits.
(2) When a data packet is received following the setup packet, the USB request parameters are stored in the
(1) Control read transfers:
(2) Control write transfers and no-data control transfers:
(1) bmRequestType
(2) wIndex
(3) wLength
(4) wValue
(5) wValue ≠ 0 and DVSQ
(6) wValue = 0 and DVSQ
O c t 1 7 , 2 0 0 8
following registers: USBREQ , USBVAL , USBINDX and USBLENG .
The controller sends a zero-length packet and receives an ACK response from the USB Host Controller.
The controller receives a zero-length packet from the USB host and sends an ACK response.
(a) Sets INTSTS0 register VALID bit to “1”.
(b) Sets DCPCTR register PID bit to “NAK”.
(c) Sets DCPCTR register CCPL bit to “0”.
p a g e 1 4 6 o f 1 8 3
≠ “0x00”
≠ “0x00”
≠ “0x00”
> “0x7F”
= "011"
= "001"