R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 176

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
4.11.4 DMA access timing (Cycle steal transfer, when a multiplex bus is set)
4.11.4.1 DMA cycle steal transfer write timing (CPU multiplex bus settings: DFORM=000)
4.11.4.2 DMA Cycle steal transfer read timing (CPU Multiplex bus setting:DFORM=000)
Note 4-1: The control signal when writing data is a combination of CS_N, WR0_N, and WR1_N.
Note 4-2: The control signal when reading data is a combination of CS_N and RD_N.
Note 4-3: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to
fall when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open.
Note 4-4 : When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)".
Note 4-5: The time required until DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis
(CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings.
R e v 1 . 0 1
AD6-AD1 /
DREQi_N
DENDi_N
DREQi_N
Note 4-1
DENDi _N
WR1_N,
Note 4-3
O c t 1 7 , 2 0 0 8
Note 4-2
Note 4-4
WR0_N
D15-D0
D15-A0
A6-A1 /
CS_N
(i=0,1)
(i=0,1)
(i=0,1)
Note 4-3
CS_N
RD_N
(i=0,1)
ALE
ALE
32
ta (CTRL - DendV) 11
tsu (A - ALE)
p a g e 1 7 6 o f 1 8 3
tw (ALE)
37
determination
32
Address
tdwr (ALE - CTRL)
36
25
37
tsu (A - ALE) th (A - ALE)
36
tw (ALE)
tdwr (ALE - CTRL)
tdis (PCTRLH - Dreq)
th (A - ALE)
determination
Address
35
17
17
Data determination
DENDi_N determination
tdis (CTRL - Dreq)
tdis (CTRL - Dreq)
tw (CTRL)
tsu (D)
45
ta (CTRL - D) 3
ten (CTRL - D) 5
35
tsu (DEND)
twr (CTRL) 42
Data determination
determination
Note 4-5
39
43
DENDi_N
38
ten (CTRL - Dreq)
th (D)
th (DEND)
trec (ALE)
twh (Dreq)
19
twh (Dreq)
tv (CTRL - DendV)
44
ten (CTRL - Dreq)
tdis (CTRL - D) 6
46
20
tv (CTRL - D)
determination
Address
20
19
trec (ALE) 38
12
4