R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 43

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
Remarks
None
2.8.9
R e v 1 . 0 1
♦ D0FIFO port selection register [D0FIFOSEL]
♦ D1FIFO port selection register [D1FIFOSEL]
RCNT REW DCLRM DREQE
7-4 Unassigned. Fix to "0".
3-0
Bit
15
14
13
12
11
10
9
8
15
0
-
RCNT
Read count mode
REW
Buffer pointer rewind
DCLRM
This is the auto buffer memory
clear mode accessed after the
data for the specified pipe has
been read.
DREQE
DREQ signal output enabled
Unassigned. Fix to "0".
MBW
FIFO port access bit width
Nothing is assigned. Fix to "0".
BIGEND
FIFO port endian control
CURPIPE
FIFO port access pipe
specification
Read count mode (RCNT)
When "1" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit
is read (for a double buffer, when the data on one side is read), the controller clears the DxFIFOCTR register DTLN bit
to "0".
When "1" is written to this bit, the controller counts the DxFIFOCTR register DTLN bits each time during the reception
data read of the FIFO buffer assigned to the specified pipe.
Write "0" to this bit to access DxFIFO by writing "1" to the BFRE bit.
14
0
-
O c t 1 7 , 2 0 0 8
13
0
-
Name
12
0
-
p a g e 4 3 o f 1 8 3
11
?
?
Specify the read mode of Dx_FIFOCTR DTLN.
0: The DTLN bit is cleared when all the reception data has
been read
1: The DTLN bit is decremented when the reception data is
read
Specify "1" to rewind the buffer pointer.
0: Invalid
1: The buffer pointer is rewound
Specify
disabled/enabled after the data for the specified pipe has
been read.
0: Auto buffer clear mode is disabled
1: Auto buffer clear mode is enabled
Specify whether the DREQ signal is disabled/enabled.
0: Output is disabled
1: Output is enabled
Specify the FIFO port access bit width.
0: 8-bit width
1: 16-bit width
Specify the byte endian of each FIFO port.
0: Little endian
1: Big endian
0000: No specification
0001: Pipe1
0010: Pipe2
1000: Pipe8
1001: Pipe9
MBW
10
0
-
whether
9
?
?
BIGEND
8
0
-
auto
Function
buffer
7
?
?
6
?
?
memory
5
?
?
clear
4
?
?
is
Software Hardware Remarks
R(0)/W
3
?
?
R/W
R/W
R/W
R/W
R/W
R/W
2
0
-
R/W(0)
CURPIPE
<Address: 2CH>
<Address: 28H>
R
R
R
R
R
R
1
0
-
0
0
-