R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 140

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.4.3.3 DEND Pint
3.4.3.4 DxFIFO Automatic Clear Mode (DxFIFO port read direction)
R e v 1 . 0 1
PKTM
0
1
Buffer state when packet received
Buffer full
Zero-Length packet received
Normal short packet received
Transaction count end
*1)
Table 3.19 Correspondence of Packet Receive and Buffer Memory Clear Process by Software
The controller can end a DMA transfer using the DEND pin. The DEND pin also functions as input/output according to
the USB data transfer direction.
When a data read event of the controller buffer memory is completed with setting DxFIFOSEL register DCLRM bit to
“1”, the buffer memory of the corresponding pipe is automatically cleared.
Table 3.19 shows the correspondence between the packet received and the buffer memory clear process by software
in each setting.
As indicated in Table 3.19, the buffer clear conditions differ according to the BFRE bit set value, even for statuses in
which clear is normally required, using the DCLRM bit eliminates the need for buffer clear by software, enabling DMA
transfers without the use of software.
Note that this function only has supports the buffer memory read direction setting.
Event
The DREQ signal is not asserted if a zero-length packet is received when the buffer is empty.
(1) Buffer memory read direction
The DEND pin can perform as an output pin and notify the external DMA controller of the last data transfer. The
DEND signal assert conditions can be set in the DMAxCFG register PKTM bit. Table 3.18 provides a list of DEND
pin asserts.
(2) Buffer memory write direction
The DEND pin becomes an input pin and the buffer memory goes to send-enabled (same status as when
“BVAL=1”) when an active edge is detected.
O c t 1 7 , 2 0 0 8
Transaction
Count End
Assert
Assert
Register Setting
p a g e 1 4 0 o f 1 8 3
BRDY
generated due
to packet
receive
No assert
Assert
Table 3.18 DEND Pin Assert List
Clear unnecessary
Clear necessary
Clear unnecessary
Clear unnecessary
BFRE=0
Receive short
packet other than
zero-length
Assert
Assert
DCLRM = 0
Clear unnecessary
Clear necessary
Clear necessary
Clear necessary
BFRE=1
Receive
Zero-Length
packet when buffer
is not EMPTY
Assert
Assert
Clear unnecessary
Clear unnecessary
Clear unnecessary
Clear unnecessary
BFRE=0
DCLRM=1
Assert
No assert
Receive zero-length
packet when buffer
is EMPTY *2)
Clear unnecessary
Clear unnecessary
Clear unnecessary
Clear unnecessary
BFRE=1