R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 86
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R8A66597BG
Manufacturer Part Number
R8A66597BG
Description
ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R8A66597BG.pdf
(185 pages)
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R8A66597FP/DFP/BG
2.16.4 Double buffer mode bit (DBLB)
2.16.5 Continuous transfer mode bit (CNTMD)
R e v 1 . 0 1
Table 2.16 Relation Between Transmission/Reception Completion Determination for the CNTMD Setup
Setup value
CNTMD bit
0
1
This bit is valid when Pipe1 to Pipe5 are selected and the transfer type of the selected pipe is set to bulk.
According to the setup value of this bit, this controller determines transmission/reception completion for the FIFO buffer
assigned to the selected pipe, as shown in Table 2.16.
This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written to.
This bit is valid when the selected pipe is Pipe1 to Pipe5.
When the software writes "1" to this bit, for the selected pipe the controller assigns the FIFO buffer size equal to two
sides specified by the PIPEBUF register BUFSIZE bit. In other words, the size of the FIFO buffer that is assigned by
the controller to the selected pipe is given below.
(BUFSIZE+1)*64*(DBLB+1) [Byte]
When the software writes "1" to this bit, and the selected pipe is used in transmission (written to "DIR bit=1"), the
controller does not issue a BRDY interrupt. Refer to the PIPEBRDY interrupt register for details.
This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. Execute
USB communication using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0",
clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three
registers.
Check that "CSSTS=0" and "PBUSY=0", modify the PID bit of the selected pipe from "BUF" to "NAK" and then modify
this bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to use the software to
check the PBUSY bit.
O c t 1 7 , 2 0 0 8
If the reception has been written ("DIR=0"), the condition when the status of the FIFO buffer changes to
Read Possible. When the controller has received one packet.
If transmission direction has been written ("DIR=1"), the condition when the status of the FIFO buffer
changes to Transmission Possible. When following conditions are fulfilled:
(1) The software (or DMAC) has written the data of maximum packet size in the FIFO buffer.
(2) The software (or DMAC) has written the data of short packet (including the case of 0 byte) and
"BVAL=1".
If the reception direction has been written ("DIR=0"), conditions for the FIFO buffer to change to Read
Enabled status are:
(1) When the number of bytes of received data in the specified FIFO buffer of the selected PIPE matches the
(2) When the controller receives a short packet other than a zero-length packet
(3) When the contoller receives a Zero-Length packet even though data is already stored in the specified
FIFO buffer of the selected PIPE.
(4) When the controller receives packets as many as the transaction counter set for the selected pipe.
If the transmission direction has been written ("DIR=1"), the condition when the status of the FIFO buffer
changes to Transmission Possible. When (1), (2) or (3) from the following conditions is fulfilled:
(1) When the data count written by the software (or DMAC) does not match with one side of FIFO buffer size
(2) When the software (or DMAC) writes the data (including 0 bytes) smaller than the data on one side of
(3) When the software writes the data (including 0 bytes) smaller than the data on one side of FIFO buffer
set number of bytes ((BUFSIZE+1)*64)
assigned to the selected pipe and asserts the DENDx_N signal simultaneously with write of the data for the
last time.
FIFO buffer assigned to the selected pipe and "BVAL=1".
assigned to the selected pipe.
p a g e 8 6 o f 1 8 3
Read Possible status and method to determine transmission possibility
Value and the FIFO Buffer
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