R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 19

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.5.1 Host Controller function selection
R e v 1 . 0 1
XIN clock selection bit (XTAL)
In this bit, write the value corresponding to the quartz crystal or oscillator connected to the XIN pin. This controller
determines the increasing multiples of 48MHz PLL according to the setup value of this bit.
This bit is set immediately after a hardware reset. Do not modify it during controller operations.
Oscillation buffer enable bit (XCKE)
Write "1" to this bit to enable the oscillation buffer operations of this controller. Write "0" to disable the oscillation buffer
operations.
Do not write "XCKE=0" for the time (time when "CNTFLG=1" is displayed) when clock restoration process is carried out
by the controller. Write "XCKE=1" to end the clock restoration process.
48MHz PLL operations enabled bit (PLLC)
Write "1" to this bit to enable this controller’s 48MHz PLL operations. Write "0" to disable them.
USB block clock enabled bit (SCKE)
Write "1" to this bit to enable this controller’s clock supply to the USB block. Write "0" to disable it.
When "0" is written to this bit, the registers that can be written to are shown in Table 2.3. Other registers cannot be
written. Each register can be read when "0" is written to this bit.
Hi-Speed operations enabled bit (HSE)
Write "1" to this bit to enable Hi-Speed operations for Port0. When "HSE=1" is written, this controller operates Port0
with Hi-Speed or Full-Speed depending on the reset handshake result.
When "HSE=0" is written, the port operates at Low-Speed or Full-Speed. When it is detected that a Low-Speed
peripheral device is attached to the port, always write "HSE=0". When "HSE=1" is written, this controller executes the
reset handshake protocol and, depending on its result, the port operates at Hi-Speed or Full-Speed automatically.
This bit can be modified "after attach detection (ATTCH interrupt detection) and before the USB bus reset (before
writing "USBRESET=1")".
O c t 1 7 , 2 0 0 8
Table 2.3 List of Registers That Can Be Written by the Software When "SCKE=0"
p a g e 1 9 o f 1 8 3
Address
0EH
00H
02H
Register name
SYSCFG0
SYSCFG1
PINCFG