CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 20

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

1.0 Pin Descriptions
Table 1-1. Hardware Signal Definitions (4 of 5)
1-8
RLOS [1:4]
LLOOP [1:4]
RLOOP [1:4]
TDO
TDI
TMS
TCK
TRST
CS
SDI
SDO
SCLK
VAA
GND
VAAT[1:4]
GNDT[1:4]
VAAR
GNDR
Pin Label
Receive Loss of
Signal
Local Loop
Remote Loop
Test Data Output
Test Data Input
Test Mode Select
Test Clock
Reset
Chip Select
Serial Data In
Serial Data Out
Serial Clock
Analog Supply
Ground
Tx Driver Supply
Ground
Rx Analog Supply
Ground
Signal Name
Power Supply Pins and No-Connect Pins
O
I/O
I
I
I
I
I
I
P
P
P
P
I
I
I
O
O
Boundary Scan Signals (JTAG)
I
I
I
P
P
P
P
P
Host Serial Control Signals
Advance Information
RLOS is asserted low when 100 (T1) or 32 (E1) consecutive 0s (no
pulses) are received at the line interface or when the received signal level
is approximately 18 dB below nominal for at least 1 ms.
These pins are always enabled in Hardware Mode and may be enabled or
disabled in Host Mode [LIU_CTL; addr n3]. A low on LLOOP initiates Local
Analog Loopback and a low on RLOOP initiates Remote Line Loopback.
Local Digital Loopback is initiated if both signals are asserted together.
Test data output per IEEE Std. 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic.
Updated on the falling edge of TCK.
Test data input per IEEE Std. 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of
TCK. TDI may be left unconnected if not used.
Active-low test mode select input per IEEE Std 1149.1-1990. Internally
pulled-up input signal used to control the test logic state machine.
Sampled on the rising edge of TCK. TMS may be left unconnected if not
used.
Test clock input per IEEE Std. 1149.1-1990. Used for all test interface and
internal test-logic operations. If not used, TCK should be pulled low.
Active low reset. TRST is pulled up internally and may be left unconnected
if not used.
In Host Mode, CS is an active low input used to enable read/write access
with the host serial control port. CS /JSEL(1) is a dual function pin.
In Host Mode, SDI is the serial data input for the host serial control port.
SDI/JSEL(2) is a dual function pin.
In Host Mode, SDO is the serial data output for the host serial control port.
SDO/JATERR[1] is a dual function pin.
In Host Mode, SCLK is the serial clock input for the host serial control
port. SCLK/JDIR is a dual function pin.
+3.3 V + 5%. Power supply pair for the analog circuitry.
+3.3 V + 5%. Power supply pairs for the transmitter driver circuitry. These
pin pairs should each be bypassed with a tantalum capacitor value of at
least 10 F.
+ 3.3 V + 5%. Power supply pair for the analog receiver circuitry.
Conexant
Definition
Quad T1/E1 Line Interface
N8380DSA
CN8380