CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 55

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8380
Quad T1/E1 Line Interface
3.2 Global Control and Status Registers
DID[7:4]
DID[3:0]
RESET
G_T1/E1N
CPD_IE
TCLK_I/O
N8380DSA
4/21/99
00—Device Identification (DID)
01—Global Configuration (GCR)
CLK_OE
DID[7]
RESET
7
7
Device ID
Device Revision
G_T1/E1N
Global Reset
configuration registers to their default values for all four ports. Also, several output pins are
three-stated. After RESET is complete, the following is true:
•
•
•
•
•
•
Global Clock Mode
operate in a mode which insures the minimum output jitter on the CLK1544 output or the CLK
2048 output.
Clock Output Enable
outputs.
CLAD Phase Detector Error Interrupt Enable
CPD_INT [CSTAT; addr 06], to generate an interrupt request.
Transmit Clock Input/Output
DID[6]
0 = CLK2048 output jitter minimized
1 = CLK1544 output jitter minimized
0 = Clock outputs are three-stated
1 = Clock outputs are enabled
0 = Interrupt disabled
1 = Interrupt enabled
0 = TCLK[1:4] pins are inputs
1 = TCLK[1:4] pins are outputs
6
6
Digital receiver outputs (RPOSO[1:4], RNEGO[1:4], RCKO[1:4]) are three-stated.
Transmitter line outputs (XTIP[1:4], XRING[1:4]) are three-stated.
CLK1544, CLK2048, and CLADO clock outputs are three-stated.
Transmitter clocks, TCLK[1:4] are configured as inputs.
All interrupt sources are disabled.
All configuration registers are set to default values.
—
CLK_OE
DID[5]
When written to 1, initiates an internal global reset process which sets all
5
5
—
—
This bit selects one of two CLAD operating modes. The CLAD can
Determines output state of CLK1544, CLK2048, and CLADO clock
Advance Information
CPD_IE
DID[4]
—
4
4
Determines whether TCLK[1:4] pins are inputs or outputs.
Conexant
TCLK_I/O
DID[3]
3
3
—
Enables CLAD loss of lock detector,
CMUX[2]
DID[2]
2
2
3.2 Global Control and Status Registers
CMUX[1]
DID[1]
1
1
3.0 Registers
CMUX[0]
DID[0]
0
0
R/W
3-3
R