CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 25

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8380
Quad T1/E1 Line Interface
2.2.1 Hardware Mode
2.2.2 Host Mode
2.2.3 Host Serial Control Interface
N8380DSA
2.2 Configuration and Control
In Hardware Mode, the device is controlled using dedicated hardware control
pins. In this mode, the four channels are configured globally to identical
operating modes (T1, E1, transmit termination, jitter attenuators, and so on). Each
channel has device pins dedicated for channel control and status, such as
loopback controls, bipolar/unipolar interface modes, and loss of signal indicators.
Refer to
pins. Hardware Mode is selected by pulling the HM pin high.
In Host Mode, control of the device is through a four-line serial port. In this
mode, all control and status functions can be accessed using internal registers.
Refer to
selected by grounding the HM pin.
The CN8380 serial interface is a four-wire, slave interface which allows a host
processor or framer with a compatible master serial port to communicate with the
LIU. This interface allows the host to control and query the CN8380 status by
writing and reading internal registers. One 8-bit register in the LIU can be written
via the SDI pin or read from the SDO pin at the clock rate determined by SCLK.
The serial port is enabled by pulling the chip select pin,
the read and write cycles. Refer to
During a write or read operation, an 8-bit control word, consisting of a read/write
control bit (R/W) and a 7-bit LIU register address (A[6:0]) is transmitted to the
LIU using the SDI pin. If the operation is a write operation (R/W = 0), an 8-bit
register data (D[7:0]) byte follows the address on the SDI pin. This data is
received by the CN8380 and stored in the addressed register. If the operation is a
read operation (R/W = 1), the CN8380 outputs the addressed register contents on
the SDO pin. The signal input on SDI is sampled on the SCLK falling edge, and
data output on SDO changes on the SCLK rising edge.
The serial interface uses a 16-bit process for each write or read operation.
Table 1-1, Hardware Signal
Chapter 3.0,
Advance Information
Conexant
Registers, for a description of each register. Host Mode is
Figure 2-2
Definitions, for a description of all hardware
for host serial port signals.
2.2 Configuration and Control
CS
, active (low) during
2.0 Circuit Description
2-3