CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 31

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8380
Quad T1/E1 Line Interface
2.3.4 RZCS Decoder
2.3.5 Receive Digital Interface
N8380DSA
2.3.5.2 Unipolar Mode
2.3.5.1 Bipolar Mode
path, RCKO is replaced with the jitter attenuated clock. The JAT performance is
discussed in
put in the receive path by setting JEN and JDIR register bits to 1 [JAT_CR; addr
n0]. In Hardware Mode, the JAT is configured for all channels globally using the
JSEL(2:0) and JDIR pins. Refer to
The RZCS decoder decodes the dual-rail data from the data slicer or from the JAT.
In T1 mode, the RZCS decoder replaces received B8ZS codes with eight 0s. In E1
mode, HDB3 codes are replaced with four 0s. The B8ZS code is 000VB0VB and
the HDB3 code is X00V; where B is a normal AMI pulse, V is a bipolar violation,
and X is a don't-care.
mode is unipolar. In Host Mode, RZCS decoding (and TZCS encoding) is enabled
for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In
Hardware Mode, ZCS encoding/decoding is controlled globally for all channels
by pulling the ZCS pin high. For the Hardware Mode pin definition, see
Table
The digital receiver outputs are provided on the RPOSO[n], RNEGO[n], and
RCKO[n] pins, where [n] is channel number 1 to 4. The receiver outputs can be
configured to operate in two modes: Bipolar NRZ format or unipolar NRZ
format. In both modes, RPOSO[n] and RNEGO[n] outputs are clocked by
RCKO[n], the recovered line rate clock, or the jitter attenuated clock if the JAT is
enabled in the receive path. RCKO[n] polarity is configurable by the CLK_POL
pin in Hardware Mode or register bit CLK_POL [RLIU_CR; addr n1] in Host
Mode. RPOSO[n], RNEGO[n], and RCKO[n] are three-stated during device
reset.
In bipolar mode, RPOSO/RNEGO signals output received data in bipolar
dual-rail format, where a high level on RPOSO indicates receipt of a positive
AMI pulse, and a high level on RNEGO indicates receipt of a negative AMI pulse
on RTIP/RING inputs. In bipolar mode, the RZCS decoder is not available. In
Hardware Mode, bipolar operation is enabled globally for all channels by pulling
the UNIPOLAR pin low. In Host Mode, bipolar operation is enabled per channel
by writing a 0 to register bit UNIPOLAR [RLIU_CR; addr n1].
In unipolar mode, RPOSO/RNEGO signals are replaced by RDATO/BPV signals.
AMI encoded received data is decoded and output on RDATO in NRZ format,
and BPV indicates that the currently received bit is a bipolar violation. If the
RZCS decoder is enabled, the BPV pin indicates only bipolar violations which are
not part of a ZCS code (B8ZS or HDB3). In Hardware Mode, unipolar operation
is enabled by pulling the UNIPOLAR pin high. In Host Mode, unipolar operation
is enabled by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
In Host Mode, the JAT is configured for each channel independently and is
ZCS decoding (and encoding) can be enabled only if the digital interface
1-1.
Section 2.6, Jitter
Advance Information
Conexant
Attenuator.
Chapter 1.0, Pin Descriptions
2.0 Circuit Description
for details.
2.3 Receiver
2-9