CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 47

no-image

CN8380EPF

Manufacturer Part Number
CN8380EPF
Description
integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
CN8380
Quad T1/E1 Line Interface
Figure 2-10. CLAD Block Diagram
N8380DSA
CLADI
Labels in brackets [ ] refer
to register bits.
Refer to the following registers:
Global Configuration; addr 01
CLAD Configuration; addr 02
CLAD Frequency Select; addr 03
CLAD Phase Detector Scale Factor; addr 04
CLAD Status; addr 06
RCKO[1]
RCKO[2]
RCKO[3]
RCKO[4]
Device I/O Pin
Monitor
Clock
2.7 Clock Rate Adapter
The CLAD uses an input clock reference at a particular frequency (8 kHz to
16,384 kHz) to synthesize output clocks at a different frequency (8 kHz to 16,384
kHz). The CLAD outputs are frequency-locked to the selected timing reference.
The CLAD can operate with input reference frequencies at multiples and
submultiples of T1 or E1 line rates. The CLAD block diagram is illustrated in
Figure
÷ [RSCALE] Factor
÷ [VSCALE] Factor
CLADR
CLADV
Detector
Phase
2-10.
Clock Rate Adapter (CLAD)
Advance Information
[LFGAIN]
Loop
Filter
Conexant
13
[G_T1/E1N]
[CPD_IE]
Divider Chain
[FREE]
NCO
CLAD Control/
32.768 MHz
2.048 MHz
1.544 MHz
14
Status
10 MHz
[CLK_OE]
[CPDERR]
[CPD_INT]
2.0 Circuit Description
2.7 Clock Rate Adapter
CLK2048
CLK1544
CLADO
CLK32
REFCKI
2-25

Related parts for CN8380EPF