CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 34

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Circuit Description
2.4 Transmitter
Table 2-2. Transmitter Operating Modes
2-12
NOTE(S):
(W/LLOOP=0)
RLOOP
0
0
0
0
0
0
1
1
X is don’t-care.
TLOC
X
X
X
0
1
1
X
X
Configuration and Input Status
TAIS
If TCLK[n] is not present (for two clock periods), the alternate AIS clock on
either TACKI (T1 Mode) or EACKI (E1 Mode) is used. The AIS transmit clock
switches back to TCLK[n] when the TCLK[n] signal returns.
TAIS register bit, or automatically by enabling the AUTO_AIS register bit. AIS
clock switching can be enabled by using the AISCLK register bit. Setting
AISCLK to 1 forces the use of the alternate AIS clock on either TACKI (T1
Mode) or EACKI (E1 Mode) pins when transmitting AIS. If AUTO_AIS is set
to 1, AIS is automatically transmitted when the clock monitor detects loss of
clock on TCLK[n]. When using automatic AIS transmission, the user should also
enable the AISCLK bit and provide an alternate clock source to insure that AIS
will be transmitted. CLAD output clocks CLK2048 and CLK1544 can be
connected externally to EACKI and TACKI alternate AIS clock inputs for this
purpose. Setting register bit TAIS_PE to 1 disables the TAIS register bit and
allows manual transmission of AIS using the
LIU_CTL [addr n3] in
Definitions.
using the received clock (or JCLK if the JAT is enabled in the receive direction).
Table 2-2
settings and input conditions.
In Hardware Mode, AIS can be controlled only manually by pulling the
In Host Mode, AIS can be transmitted using the
If TAIS is activated when Remote Line Loopback is active, AIS is transmitted
[n] hardware pin low. If TCLK[n] is present, then it is used to transmit AIS.
TAIS
0
1
1
0
0
0
0
1
lists transmitter operating modes resulting from various configuration
Advance Information
AUTO_AIS
Conexant
0
X
X
1
1
1
X
X
Chapter 3.0,
AISCLK
Registers, and to
X
0
1
X
0
1
X
X
TAIS
Tx Data
AIS
AIS
Tx Data
AIS
AIS
Rx Data
AIS
Transmit
[n] hardware pins. Refer to
Data
TAIS
Table 1-1, Hardware Signal
Transmitter Mode
Quad T1/E1 Line Interface
[n] hardware pins or the
TCLK
TCLK
TACKI/EACKI
TCLK
TCLK
TACKI/EACKI
RCLK
RCLK
Transmit
Clock
N8380DSA
CN8380