CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 27

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8380
Quad T1/E1 Line Interface
N8380DSA
2.2.4.1 Power-on Reset
2.2.4.2 Hard Reset
2.2.4.3 Soft Reset
An internal power-on reset process is initiated during power-up. When VDD has
reached approximately 2.6 V , the internal reset process begins and continues for
300 ms maximum if REFCLK is applied. If REFCLK is not present, the CN8380
remains in the reset state.
Hard reset is initiated by bringing the
internal reset process completes in 5 s maximum. If the
continuously, the clock and data outputs and the
following output pins are forced to high impedance while
In Host Mode, soft reset is initiated by writing a one to the RESET bit in the
Global Configuration register [addr 01]. The RESET bit is self-clearing. Once
initiated, the internal reset process completes in 5 s maximum and the device
enters normal operation.
CLK1544, CLK2048, and CLADO
clock outputs are enabled.
Transmitter clocks, TCLK[1:4], are
configured as inputs.
The
by DPM).
RPOSO[1:4]
RNEGO[1:4]
RCKO[1:4]
XTIP[1:4]
XRING[1:4:]
CLK1544
CLK2048
IRQ
pin is enabled (controlled
Hardware Mode
Advance Information
Conexant
CLADO
TCLK[1:4]
RLOS[1:4]
JATERR[1:4]
SDO
TDO
IRQ
RESET
CLK1544, CLK2048, and CLADO
clock outputs are three-stated.
Transmitter clocks, TCLK[1:4], are
configured as inputs.
The
All interrupt sources are disabled.
All configuration registers are set to
default values as listed in
Address
pin active (low). Once initiated, the
IRQ
IRQ
Map.
pin is three-stated.
pin remain three-stated. The
2.2 Configuration and Control
Host Mode
RESET
RESET
2.0 Circuit Description
pin is held active
is held active:
Section 3.1,
2-5