CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 42

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Circuit Description
2.5 Loopbacks
2.5.1 Local Analog Loopback
2.5.2 Local Digital Loopback
2-20
2.5 Loopbacks
Three per-channel loopbacks are provided for system diagnostic testing: Local
Analog Loopback, Local Digital Loopback, and Remote Line Loopback.
Loopbacks can be controlled by either hardware pins or internal register bits. For
hardware control, two dedicated pins—
configured in Host Mode, register bits are provided for loopback control. In
addition, the
loopbacks can be controlled by the hardware pins even in Host Mode. Loopback
controls are detailed in
Chapter 3.0,
Table 2-9. Loopback Control Pins
Local Analog Loopback (LAL) causes the transmit data and clock inputs
(TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs
(RPOSO/RNEGO and RCKO). This loopback connects an internal copy of the
analog transmit signal (XTIP and XRING outputs) to the receiver input, so that
virtually all of the device circuitry can be tested. While LAL is active, transmit
data continues to be transmitted on XTIP and XRING, but RTIP and RRING
inputs are ignored. Applying a high on the
is active disables the transmitter outputs and causes an RLOS.
Local Digital Loopback (LDL) causes the transmit data and clock inputs
(TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs
(RPOSO/RNEGO and RCKO). This loopback includes the JAT (if enabled) but
does not include the line transmit and receive circuitry. Consequently, XTIP and
XRING transmitter outputs are unaffected, and receiver RTIP and RRING inputs
remain connected to the line to monitor for RLOS. Also, the AIS (all 1s)
generator is not included in the loopback path so that AIS can be transmitted
toward the line while simultaneously providing a local loopback.
LLOOP
1
1
0
0
Registers.
LLOOP
Advance Information
Conexant
and
RLOOP
Table
RLOOP
1
0
1
0
2-9. Refer also to register LIU_CTL [addr n3] in
pins can be enabled by register bits so that
None
Remote Line Loop
Local Analog Loop
Local Digital Loop
LLOOP
XOE
and
pin when Local Analog Loopback
RLOOP
Loopback
Quad T1/E1 Line Interface
—are provided. If
N8380DSA
CN8380