CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 62

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.0 Registers
3.3 Per Channel Registers
3.3 Per Channel Registers
T1/E1
JEN
JDIR
JCENTER
JSIZE[2:0]
3-10
10, 20, 30, 40—Jitter Attenuator Configuration (JAT_CR)
T1/E1
7
T1/E1 Select
All configuration register settings should be re-initialized after changing the T1/E1 control bit.
T1/E1 selects the nominal line rate (shown below), while the exact receive and transmit line
rate frequencies are independently determined by their respective input clock or data
references. The actual receive and transmit line frequency can vary within defined tolerances.
Jitter Attenuator Enable
by JDIR bit).
Select JAT Path—Applicable only when the JAT is enabled (see JEN description). JAT elastic
store is placed in either the receive or transmit path.
Force JAT to Center
the elastic store read pointer to one-half the programmed JSIZE. JCENTER is typically written
at power-up. JCENTER can optionally be asserted after recovery from a loss of signal (RLOS
or RALOS) or in response to a transmit loss of clock (TLOC), or after recovering from a
persistent JAT elastic store error (JERR). The JCENTER bit is self clearing.
JAT Elastic Store Size—Selects the maximum depth of the JAT elastic store. The 32-bit depth
is sufficient to meet jitter attenuation requirements in all cases where the JAT cutoff frequency
is programmed at 6 Hz. However, in cases where an external reference is selected or a narrow
loop bandwidth is programmed, the elastic store depth can tolerate up to 64 UI (128 bits) of
accumulated phase offset.
—
0 = 2.048 MHz line rate (E1)
1 = 1.544 MHz line rate (T1)
0 = Disable JAT
1 = Enable JAT
0 = JAT in TX path
1 = JAT in RX direction, jitter attenuated recovered clock output on RCKO
0 = normal operation
1 = recenter JAT elastic store
6
JSIZE
000
001
010
011
1xx
—
Enables receive and transmit circuits to operate at either the T1 or E1 line rate.
JEN
5
—
Writing a 1 to JCENTER resets the elastic store write pointer and forces
Elastic Store Size
—
JEN enables the JAT in the receive or the transmit path (determined
128 Bits
16 Bits
32 Bits
64 Bits
Advance Information
8 Bits
JDIR
4
Conexant
JCENTER
3
JSIZE[2]
2
Quad T1/E1 Line Interface
JSIZE[1]
1
N8380DSA
JSIZE[0]
CN8380
4/21/99
0
R/W