CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet - Page 30

• Manufacturer Part Number: CN8380EPF
• Description: integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Circuit Description
2.3 Receiver
2.3.2 Clock Recovery
2.3.2.1 Phase Lock Loop
2.3.3 Receive Jitter Attenuator
2-8
2.3.2.2 Jitter Tolerance
2.3.1.4 Loss Of Signal
Detector
The Receive Loss of Signal (RLOS) Detector monitors both consecutive 0s and
signal level. Receive Analog Loss Of Signal (RALOS) is declared when
RTIP/RRING input signal amplitude is a certain level (RALOS level) below the
nominal receive level for at least 1 ms (2 ms maximum). RALOS status is cleared
as soon as pulses above the RALOS level are detected.
receive level is also below the SQUELCH level. Squelch is enabled in register
RLIU_CR [addr n1]. In Host Mode, RALOS real time status is reported in the
ALARM [addr n5] register; and an interrupt status bit is available in the ISR [addr
n6] register. Also, RALOS is indicated on the
NOR of the RLOS[n] status and RALOS[n] status.
are detected. RLOS status is cleared when pulses are received with at least 12.5%
pulse density (during a period of 192 bits starting with the receipt of a pulse) and
where no occurrences of 100 or 32 consecutive bits with no pulses are detected.
In Host Mode, RLOS real time status is reported in the ALARM register [addr
n5]; and an interrupt status bit is available in the ISR register [addr n6]. Also,
RLOS is indicated by a 0 level on the
the RLOS[n] status and RALOS[n] status.
The Receive Phase Lock Loop (RPLL) recovers the line rate clock from the data
slicer dual-rail outputs. The RPLL generates a recovered clock that tracks jitter in
the data and sustains the data-to-clock phase relationship in the absence of
incoming pulses. The RPLL is a digital PLL which adjusts its output phase in
1/16 unit interval (UI) steps. Consequently, the RPLL adds approximately 0.12 UI
peak-to-peak jitter to the recovered receive clock.
signal and smoothly transitions to a nominal line rate frequency determined by
the CLAD input reference (selected by CMUX [GCR; addr 01] or FREE
[CLAD_CR; addr 02]). If the CLAD reference is the recovered received clock
from a channel which has detected RLOS, the CLAD outputs and the recovered
received clock enter a “hold-over” state to maintain the average frequency that
was present just before the RLOS was detected.
Figure 2-8, Receiver Input Jitter
tolerance for all jitter attenuator (JAT) configurations: JAT disabled and JAT
enabled in the receive path with each JAT elastic store size. The jitter tolerance of
the clock and data recovery circuit alone (not including the JAT) is illustrated by
the curve labeled with “JAT Disabled.” The receiver meets jitter tolerance
specifications TR62411, G.823, and G.824. In addition, the receiver meets jitter
tolerance tests defined in ETS300 011: ISDN; Primary Rate User-Network
Interface Layer 1 Specification and Test Principles.
The data slicer outputs can be routed to the JAT before going to the RZCS
decoder. The JAT attenuates clock and data jitter introduced by the line or added
by the clock recovery circuit. The JAT can be placed in the receive path or
transmit path, but not in both simultaneously. If the JAT is placed in the receive
In Host Mode, the received data can be replaced with all 0s (squelched) if the
RLOS is declared when 100 (T1) or 32 (E1) consecutive bits with no pulses
During loss of signal (RLOS or RALOS), the RPLL maintains an output clock
Advance Information
Conexant
Tolerance, illustrates the receiver’s jitter
RLOS
[n] pin, which is the logical NOR of
RLOS
[n] pin, which is the logical
Quad T1/E1 Line Interface
N8380DSA
CN8380