M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet
M1AFS250-FGG256I
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M1AFS250-FGG256I Summary of contents
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... In Partnership with Pigeon Point Systems • ARM Cortex-M1 Enabled MicroBlade Advanced Mezzanine Card Support (U1) • Targeted to Advanced Mezzanine Card (AdvancedMC Designs) • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC) AFS090 AFS250 AFS600 M1AFS250 M1AFS600 P1AFS600 U1AFS600 90,000 250,000 600,000 2,304 6,144 ...
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... Flash Memory Blocks Analog Analog Analog Analog Analog Analog Quad Quad Quad Quad Quad Quad Bank 3 AFS090 AFS250 M1AFS250 37/9 (16) 60/16 (20) 65/15 (24) 93/26 (24) 75/22 (20) 114/37 (24 CCC SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ...
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... Fusion Devices AFS090 = 90,000 System Gates AFS250 = 250,000 System Gates AFS600 = 600,000 System Gates AFS1500 = 1,500,000 System Gates ARM-Enabled Fusion Devices M1AFS250 = 250,000 System Gates M1AFS600 = 600,000 System Gates M1AFS1500 = 1,500,000 System Gates Pigeon Point Devices P1AFS600 = 600,000 System Gates P1AFS1500 = ...
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... Cortex-M1 devices are offered in the same speed grades and packages as basic Fusion devices. • Pigeon Point devices are only offered in –2 speed grade and FG484 and FG256 packages. • MicroBlade devices are only offered in standard speed grade and the FG256 package AFS090 AFS250 M1AFS250 C, I – – – ...
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Table of Contents Fusion Device Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Fusion Device Family Overview Introduction ® The Actel Fusion mixed signal FPGA satisfies the demand from system architects for a device that simplifies design and unleashes their creativity. As the world’s first mixed signal programmable logic family, Fusion ...
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Fusion Device Family Overview with the integrated phase-locked loops (PLLs) to provide clocking support to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such as watchdog timer, the Fusion RTC can control the on-chip voltage ...
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Live at Power-Up Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplify total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion LAPU clocking (PLLs) replaces off-chip clocking ...
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Fusion Device Family Overview – RC oscillator – Crystal oscillator – No-Glitch MUX (NGMUX) • Digital I/Os with advanced I/O standards • FPGA VersaTiles • Analog components – ADC – Analog I/Os supporting voltage, current, and temperature monitoring – 1.5 ...
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The AC pad measures the voltage drop across an external sense resistor to calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The AT pad measures the load-side voltage level. ...
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Fusion Device Family Overview (×32) data port options. Through the programmable flash parallel interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations. The flash memory has built-in security. The user can configure either the entire ...
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Clock Resources PLLs and Clock Conditioning Circuits (CCCs) Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also include a ...
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Fusion Device Family Overview standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards. Each I/O module contains several input, output, ...
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Related Documents Datasheet Core8051 www.actel.com/ipdocs/Core8051_DS.pdf Application Notes Fusion FlashROM http://www.actel.com/documents/Fusion_FROM_AN.pdf Fusion SRAM/FIFO Blocks http://www.actel.com/documents/Fusion_RAM_FIFO_AN.pdf Using DDR in Fusion Devices http://www.actel.com/documents/Fusion_DDR_AN.pdf Fusion Security http://www.actel.com/documents/Fusion_Security_AN.pdf Using Fusion RAM as Multipliers http://www.actel.com/documents/Fusion_Multipliers_AN.pdf Handbook Cortex-M1 Handbook www.actel.com/documents/CortexM1_HB.pdf User’s Guides Designer User's Guide http://www.actel.com/documents/designer_UG.pdf Fusion ...
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Device Architecture Fusion Stack Architecture To manage the unprecedented level of integration in Fusion devices, Actel developed the Fusion technology stack (Figure 2-1). This layered model offers a flexible design environment, enabling design at very high and very ...
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Device Architecture The system application, Level 3, is the larger user application that utilizes one or more applets. Designing at the highest level of abstraction supported by the Actel Fusion technology stack, the application can be easily created in FPGA ...
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VersaTile Characteristics Sample VersaTile Specifications—Combinatorial Module The Fusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library Fusion, IGLOO/e and ProASIC3/E Macro Library A OR2 ...
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Device Architecture OUT GND VCCA OUT Figure 2-4 • Combinatorial Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX(t PD PD(RR) where edges are applicable for the ...
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Timing Characteristics Table 2-1 • Combinatorial Cell Propagation Delays Commercial Temperature Range Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 ...
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Device Architecture Data CLK Data CLK CLR Figure 2-5 • Sample of Sequential Cells 50% CLK 50% Data EN 50 PRE t SUE CLR Out Figure 2-6 • Sequential Timing Model and Waveforms Out Data ...
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Sequential Timing Characteristics Table 2-2 • Register Delays Commercial Temperature Range Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for the Core Register HD t ...
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Device Architecture Array Coordinates During many place-and-route operations in the Actel Designer software tool possible to set constraints that require array coordinates. are measured from the lower left (0, 0). They can be used in region constraints for ...
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Routing Architecture The routing structure of Fusion devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; high-speed very-long-line resources; and the high-performance VersaNet networks. The ultra-fast local ...
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Device Architecture Spans Four VersaTiles Figure 2-9 • Efficient Long-Line Resources 2- 10 Spans One VersaTile Spans Two VersaTiles ...
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High-Speed, Very-Long-Line Resources Pad Ring Figure 2-10 • Very-Long-Line Resources Actel Fusion Family of Mixed Signal FPGAs SRAM 16×12 Block of VersaTiles ...
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Device Architecture Global Resources (VersaNets) Fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has six CCCs. The west CCC also contains a PLL core. In the two larger devices (AFS600 ...
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Northwest Quadrant Global Network CCC CCC 6 3 CCC Southeast Quadrant Global Network Figure 2-12 • Global Network Architecture Table 2-4 • Globals/Spines/Rows by Device Global VersaNets (trees)* VersaNet Spines/Tree Total Spines VersaTiles in Each Top or ...
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Device Architecture VersaNet Global Networks and Spine Access The Fusion architecture contains a total of 18 segmented global networks that can access the VersaTiles, SRAM, and I/O tiles on the Fusion device. There are 6 chip (main) global networks that ...
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Clock Aggregation Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is ...
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Device Architecture Global Resource Characteristics AFS600 VersaNet Topology Clock delays are device-specific. global tree presented in is used to drive all D-flip-flops in the device. CCC Figure 2-15 • Example of Global Tree Use in an AFS600 Device for Clock ...
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VersaNet Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be driven ...
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Device Architecture Table 2-7 • AFS250 Global Resource Timing Commercial Temperature Range Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Maximum Skew for Global Clock RCKSW F ...
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Clocking Resources The Fusion family has a robust collection of clocking peripherals, as shown in the block diagram in Figure 2-16. These on-chip resources enable the creation, manipulation, and distribution of many clock signals. The Fusion integrated RC oscillator produces ...
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Device Architecture RC Oscillator The RC oscillator is an on-chip free-running clock source generating a 100 MHz clock. It can be used as a source clock for both on-chip and off-chip resources. When used in conjunction with the Fusion PLL ...
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Crystal Oscillator The Crystal Oscillator (XTLOSC) is source that generates the clock from an external crystal. The output of XTLOSC CLKOUT signal can be selected as an input to the PLL. Refer to Circuits" section for more details. The XTLOSC ...
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Device Architecture 1.00E-0.3 1.00E-0.4 1.00E-0.5 1.00E-0.6 1.00E-0.7 Figure 2-18 • Crystal Oscillator: RC Time Constant Values vs. Frequency (typical) Table 2-10 • XTLOSC Signals Descriptions Signal Name XTL_EN* XTL_MODE* SELMODE RTC_MODE[1:0] MODE[1:0] FPGA_EN* XTL CLKOUT Note: *Internal signal—does not exist ...
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Clock Conditioning Circuits In Fusion devices, the CCCs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations—each of the four chip corners and the middle of the east ...
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Device Architecture Clock Source Input LVDS/LVPECL Macro PADN PADP 2 INBUF Macro PAD Notes: 1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. Refer to the section on page 2-29 for signal descriptions. 2. Many specific ...
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Global Buffers with No Programmable Delays The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro driving a global buffer, hardwired together The CLKINT macro provides a global buffer function driven by the FPGA core. The CLKBUF, ...
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Device Architecture Global Buffers with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay clock input and adds a user-defined ...
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Global Input Selections Each global buffer, as well as the PLL reference clock, can be driven from one of the following 22): • 3 dedicated single-ended I/Os using a hardwired connection • 2 dedicated differential I/Os using a hardwired connection ...
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Device Architecture CCC Physical Implementation The CCC circuit is composed of the following • PLL core • 3 phase selectors • 6 programmable delays and 1 fixed delay • 5 programmable frequency dividers that provide frequency multiplication/division (not shown in ...
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PLL Macro The PLL functionality of the clock conditioning block is supported by the PLL macro. Note that the PLL macro reference clock uses the CLKA input of the CCC block, which is only accessible from the global A[2:0] package ...
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Device Architecture CCC and PLL Characteristics Timing Characteristics Table 2-12 • Fusion CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each Programmable ...
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No-Glitch MUX (NGMUX) Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses. The NGMUX is used to switch the source of a global ...
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Device Architecture The NGMUX macro is simplified to show the two clock options that have been selected by the GLMUXCFG[1:0] bits. are connected to CLK0 and CLK1 and are controlled by GLMUXSEL[1:0] to determine which signal passed ...
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Real-Time Counter System The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce power consumption in many applications. • Sleep mode, typical 10 µA • Standby mode (RTC running), typical 3 mA with 20 ...
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Device Architecture Modes of Operation Standby Mode Standby mode allows periodic power-up and power-down of the FPGA fabric. In standby mode, the real- time counter and crystal block are ON. The FPGA is not powered by disabling the 1.5 V ...
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Real-Time Counter (part of AB macro) The RTC is a 40-bit loadable counter and used as the primary timekeeping element clock source, RTCCLK, must come from the CLKOUT signal of the crystal oscillator. The RTC can be configured to reset ...
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Device Architecture Example: Calculation for Match Count To put the Fusion device on standby for one hour using an external crystal of 32.768 KHz: The period of the crystal oscillator 32.768 KHz = 30.518 ...
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Table 2-15 • Memory Map for RTC in ACM Register and Description ACMADDR Register Name 0x40 COUNTER0 Counter bits 7:0 0x41 COUNTER1 Counter bits 15:8 0x42 COUNTER2 Counter bits 23:16 0x43 COUNTER3 Counter bits 31:24 0x44 COUNTER4 Counter bits 39:32 ...
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Device Architecture Table 2-17 • VRPSM Signal Descriptions Signal Name Width Dir. VRPU VRINITSTATE RTCPSMMATCH PUB TRST* FPGAGOOD PUCORE VREN* Note: *Signals are hardwired internally and do not exist in the macro core Voltage Regulator Power-Up ...
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V Power Supply ON/OFF 3.3 V OFF VINITSTATE = 0 And PUB = 1 And TRST = 0 OFF State 3.3 V Off, PUB Pull-Up, TRST Pull-Down, VREN Disabled VRINITSTATE = 1 or PUB = 0 or TRST = ...
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Device Architecture 1.5 V Voltage Regulator The 1.5 V voltage regulator uses an external pass transistor to generate 1.5 V from a 3.3 V supply. The base of the pass transistor is tied to PTBASE, the collector is tied to ...
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Embedded Memories Fusion devices include four types of embedded memory: flash block, FlashROM, SRAM, and FIFO. Flash Memory Block Fusion is the first FPGA that offers a flash memory block (FB). Each FB block stores 2 Mbits of data. The ...
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Device Architecture Flash Memory Block Pin Names Table 2-19 • Flash Memory Block Pin Names Interface Name Width Direction ADDR[17:0] 18 AUXBLOCK 1 BUSY 1 CLK 1 DATAWIDTH[1:0] 2 DISCARDPAGE 1 ERASEPAGE 1 LOCKREQUEST 1 OVERWRITEPAGE 1 OVERWRITEPROTECT 1 PAGESTATUS ...
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Table 2-19 • Flash Memory Block Pin Names (continued) Interface Name Width Direction STATUS[1:0] 2 Out UNPROTECTPAGE 1 WD[31:0] 32 WEN 1 All flash memory block input signals are active high, except for RESET. Description Status of the last operation ...
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Device Architecture Flash Memory Block Diagram A simplified diagram of the flash memory block is shown in Output RD[31:0] MUX WD[31 :0] ADDDR[17:0] DATAWIDTH[1:0] REN READNEXT PAGESTATUS WEN ERASEPAGE PROGRAM SPAREPAGE Control AUXBLOCK Logic UNPROTECTPAGE OVERWRITEPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT PIPE ...
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Flash Memory Block Addressing Figure 2-34 shows a graphical representation of the flash memory block. Page 0 1190 140 Block Block Organization Figure 2-34 • Flash Memory Block Organization Each FB is partitioned into sectors, ...
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Device Architecture Data operations are performed in widths bytes. A write to a location in a page that is not already in the Page Buffer will cause the page to be read from the FB Array ...
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Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal. FB operations are only accepted in cycles where BUSY is logic 0. Write Operation Write operations are initiated with the assertion ...
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Device Architecture Program Operation A Program operation is initiated by asserting the PROGRAM signal on the interface. Program operations save the contents of the Page Buffer to the FB Array. Due to the technologies inherent in the FB, a program ...
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Erase Page Operation The Erase Page operation is initiated when the ERASEPAGE pin is asserted. The Erase Page operation allows the user to erase (set user data to zero) any page within the FB. The use of the OVERWRITEPAGE and ...
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Device Architecture Read Operation Read operations are designed to read data from the FB Array, Page Buffer, Block Buffer, or status registers. Read operations support a normal read and a read-ahead mode (done by asserting READNEXT). Also, the timing for ...
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The following error indications are possible for Read operations: 1. STATUS = '01' when a single-bit data error was detected and corrected within the block addressed. 2. STATUS = '10' when a double-bit error was detected in the block addressed ...
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Device Architecture Read Next Operation The Read Next operation is a feature by which the next block relative to the block in the Block Buffer is read from the FB Array while performing reads from the Block Buffer. The goal ...
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Unprotect Page Operation An Unprotect Page operation will clear the protection for a page addressed on the ADDR input initiated by setting the UNPROTECTPAGE signal on the interface along with the page address on ADDR. If the page ...
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Device Architecture Flash Memory Block Characteristics CLK RESET Active Low, Asynchronous BUSY Figure 2-44 • Reset Timing Diagram Table 2-25 • Flash Memory Block Timing Commercial Temperature Range Conditions: T Parameter t Clock-to-Q in 5-cycle read mode of the Read ...
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Table 2-25 • Flash Memory Block Timing (continued) Commercial Temperature Range Conditions: T Parameter t Page Loss Protect Setup Time for the Control Logic SUPGLOSSPRO t Page Loss Protect Hold Time for the Control Logic HDPGLOSSPRO t Page Status Setup ...
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Device Architecture FlashROM Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each bank ...
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FlashROM Characteristics HOLD Address A0 t CK2Q D0 Figure 2-46 • FlashROM Timing Diagram Table 2-26 • FlashROM Access Time Commercial Temperature Range Conditions: T Parameter Description t Address Setup Time SU t Address Hold Time HOLD ...
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Device Architecture SRAM and FIFO All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high- ...
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Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations. WD RCLK WCLK FREN FWEN CNT 12 RBLK REN ...
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Device Architecture RAM4K9 Description Figure 2-48 • RAM4K9 2- 60 RAM4K9 ADDRA11 DOUTA8 DOUTA7 ADDRA10 DOUTA0 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 DOUTB8 ADDRB10 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB ...
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The following signals are used to configure the RAM4K9 memory element: WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios Table 2-27 • Allowable Aspect Ratio Settings for WIDTHA[1:0] WIDTHA1, WIDTHA0 ...
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Device Architecture DINA and DINB These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be ...
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RAM512X18 Description Figure 2-49 • RAM512X18 Actel Fusion Family of Mixed Signal FPGAs RAM512X18 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 RW1 RW0 PIPE REN RCLK WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 WW1 WW0 WEN WCLK RESET ...
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Device Architecture RAM512X18 exhibits slightly different behavior from RAM4K9 has dedicated read and write ports. WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios Table 2-30 • Aspect ...
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Modes of Operation There are two read modes and one write mode: • Read Nonpipelined (synchronous—1 clock edge): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN ...
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Device Architecture SRAM Characteristics Timing Waveforms CLK t AS ADD t BKS BLK_B t ENS WEN_B Figure 2-50 • RAM Read for Flow-Through Output CLK t AS ADD t BKS BLK_B t ENS WEN_B DO Figure 2-51 ...
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CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-52 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ...
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Device Architecture CLK1 ADD1 DI1 CLK2 ADD2 DO2 (flow-through) DO2 (Pipelined) Figure 2-54 • One Port Write / Other Port Read Same CLK1 t AS ADD1 t DI1 CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) Figure 2-55 • ...
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CLK1 ADD1 DI1 WRO CLK2 WEN_B1 WEN_B2 ADD2 CKQ1 DO2 D n (pass-through) DO2 D (pipelined) n Figure 2-56 • Read Access After Write ...
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Device Architecture CLK1 ADD1 WEN_B1 DO1 D (pass-through) DO1 (pipelined) CLK2 ADD2 DI2 WEN_B2 Figure 2-57 • Write Access After Read onto Same Address CLK RESET_B Figure 2-58 • RAM Reset ...
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Timing Characteristics Table 2-31 • RAM4K9 Commercial Temperature Range Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup time BKS t ...
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Device Architecture Table 2-32 • RAM512X18 Commercial Temperature Range Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time ...
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FIFO4K18 Description Figure 2-59 • FIFO4KX18 Actel Fusion Family of Mixed Signal FPGAs FIFO4K18 RW2 RD17 RD16 RW1 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 ...
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Device Architecture The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios Table 2-33 • Aspect Ratio Settings for WW[2:0] ...
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FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the FULL flag goes High). A High on this signal inhibits the counting. For more information on these signals, refer to the ...
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Device Architecture FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values, respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every ...
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FIFO Characteristics Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EF AEF t RSTFG FF AFF WA/RA (Address Counter) Figure 2-60 • FIFO Reset RCLK EF AEF WA/RA NO MATCH (Address Counter) Figure 2-61 • FIFO EMPTY Flag and AEMPTY Flag ...
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Device Architecture WCLK FF AFF WA/RA NO MATCH (Address Counter) Figure 2-62 • FIFO FULL and AFULL Flag Assertion WCLK WA/RA MATCH NO MATCH (EMPTY) (Address Counter) 1st rising edge after 1st write RCLK EF AEF Figure 2-63 • FIFO ...
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Timing Characteristics Table 2-35 • FIFO Commercial Temperature Range Conditions: T Parameter t REN_B, WEN_B Setup time ENS t REN_B, WEN_B Hold time ENH t BLK_B Setup time BKS t BLK_B Hold time BKH t Input data (DI) Setup time ...
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Device Architecture Analog Block With the Fusion family, Actel has introduced the world's first mixed-mode FPGA solution. Supporting a robust analog peripheral mix, Fusion devices will support a wide variety of applications this Analog Block that separates Fusion ...
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VAREF GNDREF AV0 AC0 AT0 AV9 AC9 AT9 ATRETURN01 ATRETURN9 DENAV0 DENAC0 DENAT0 DENAV0 DENAC0 DENAT0 CMSTB0 CSMTB9 GDON0 GDON9 TMSTB0 TMSTB9 MODE[3:0] TVC[7:0] STC[7:0] CHNUMBER[4:0] TMSTINT ADCSTART VAREFSEL PWRDWN ADCRESET RTCCLK SYSCLK ACMWEN ACMRESET ACMWDATA ACMADDR ACMCLK Figure 2-65 ...
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Device Architecture Table 2-36 describes each pin in the Analog Block. Each function within the Analog Block will be explained in detail in the following sections. Table 2-36 • Analog Block Pin Description Signal Name VAREF GNDREF MODE[3:0] SYSCLK TVC[7:0] ...
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Table 2-36 • Analog Block Pin Description (continued) Number Signal Name of Bits GDON0 to GDON9 TMSTB0 to TMSTB9 DAVOUT0, DACOUT0, DATOUT0 to DAVOUT9, DACOUT9, DATOUT9 DENAV0, DENAC0, DENAT0 to DENAV9, DENAC9, DENAT9 AV0 AC0 AG0 AT0 ATRETURN01 AV1 AC1 ...
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Device Architecture Table 2-36 • Analog Block Pin Description (continued) Signal Name AG6 AT6 ATRETURN67 AV7 AC7 AG7 AT7 AV8 AC8 AG8 AT8 ATRETURN89 AV9 AC9 AG9 AT9 RTCMATCH RTCPSMMATCH RTCXTLMODE[1:0] RTCXTLSEL RTCCLK Analog Quad With the Fusion family, Actel ...
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The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG. This section is used to drive an external FET. There are two modes available: a High Current Drive mode and ...
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Device Architecture Voltage Monitor The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA industry. The Analog Quad comprises three analog input pads— Analog Voltage (AV), Analog Current (AC), and Analog Temperature (AT)—and a single ...
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The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input signals. Figure 2-68 shows the path through the Analog Quad for a signal that prescaled prior to conversion. The ...
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Device Architecture Terminology BW – Bandwidth range of frequencies that a Channel can handle. Channel A channel is define as an analog input configured as one of the Prescaler range shown in page 2-132. The channel includes ...
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Direct Digital Input The AV, AC, and AT pads can also be configured as high-voltage digital inputs pads are 12 V–tolerant, the digital input can also However, the frequency at which these pads can operate ...
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Device Architecture Current Monitor The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications. In addition to supporting the same functionality offered by the AV pad, the AC pad can be configured to monitor current across an ...
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To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB macro must be asserted low for at least t CMSTB must be asserted high for at least t must remain high until after the SAMPLE ...
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Device Architecture 0-12 V AVx Current Monitor Figure 2-73 • Positive Current Monitor Care must be taken when choosing the right resistor for current measurement application. Note that because of the 10× amplification, the maximum measurable difference between the AV ...
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Table 2-37 • Recommended Resistor for Different Current Range Measurement Current Range > – > – > – > – 100 mA > 100 mA – ...
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Device Architecture Gate Driver The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink or source and requires an ...
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C is not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can vary GS significantly during the course of a turn-on or turn-off transient. Thus, used for a first-order estimate of the switching speed of ...
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Device Architecture Temperature Monitor The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor (Figure 2-77). For improved ...
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Fusion uses a remote diode as a temperature sensor. The Fusion Temperature Monitor uses a differential input; the AT pin and ATRTN (AT Return) pin are the differential inputs to the Temperature Monitor. There is one Temperature Monitor in each ...
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Device Architecture The diode’s voltage is measured at each current level and the temperature is calculated based on where is the current when the Temperature Strobe is Low, typically 100 µA I TMSLO is the current when the Temperature Strobe ...
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Terminology Resolution Resolution defines the smallest temperature change Fusion Temperature Monitor can resolve. For ADC configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12-bit mode, the Temperature Monitor can still only resolve ...
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Device Architecture Pads AV0 AC0 Analog AG0 AT0 Quad 0 ATRETURN01 AV1 Analog AC1 AG1 Quad 1 AT1 AV2 AC2 Analog AG2 Quad 2 AT2 ATRETURN23 AV3 Analog AC3 Quad 3 AG3 AT3 AV4 AC4 Analog AG4 AT4 Quad 4 ...
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ADC Input Multiplexer At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels are user definable. Two of these channels are hardwired internally. Channel 31 connects to an internal temperature diode ...
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Device Architecture Table 2-39 • Analog MUX Channels (continued) Analog MUX Channel Table 2-40 • Channel Selection Channel Number ...
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ADC Description The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use models. Figure 2-81 shows a block diagram of the Fusion ADC. • Configurable resolution: 8-bit, 10-bit, and 12-bit mode ...
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Device Architecture ADC Configuration Description The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in The output of the ADC is the ...
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SAMPLE Table 2-43 • STC Bits Function Name Bits STC [7:0] Sample time is computed based on the period of ADCCLK. The second phase is called the distribution phase. During distribution phase, the ADC computes ...
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Device Architecture From Table 2-47 on page calculation will first compute the post-calibration time, second the distribution time, and finally the STC setting. Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be enabled and the post-calibration time, ...
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ADC Operation Description The ADC can be powered down independently of the FPGA core additional control or for power- saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the comparators in the ...
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Device Architecture Timing Diagram SYSCLK t RECCLR ADCRESET TVC[7:0] CALIBRATE Note: *Refer page 2-104 Figure 2-82 • Power-Up Calibration Status Signal Timing Diagram SYSCLK ADCSTART MODE[3:0] TVC[7:0] STC[7:0] VAREF CHNUMBER[7:0] Figure 2-83 • Input Setup Time ...
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SYSCLK t SUADCSTART ADCSTART BUSY SAMPLE DATAVALID ADC_RESULT[11:0] Notes: 1. Refer page 2-104 for the calculation on the sample time See page 2-106 for calculation on the conversion time ...
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Device Architecture SYSCLK ADCRESET ADCSTART BUSY SAMPLE t CLR2QVAL DATAVALID t CK2QCAL CALIBRATE Interrupts Power-Up Calibration Note: * See page 2-98 Figure 2-86 • Injected-Conversion Timing Diagram CK2QBUSY t t CK2QSAMPLE CK2QSAMPLE t ...
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ADC Interface Timing Table 2-45 • ADC Interface Timing Commercial Temperature Range Conditions: T Parameter t Mode Pin Setup Time SUMODE t Mode Pin Hold Time HDMODE t Clock Divide Control (TVC) Setup Time SUTVC t Clock Divide Control (TVC) ...
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Device Architecture Terminology Conversion Time Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one ...
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Gain Error The gain error of an ADC indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB percent of full-scale (%FSR). ...
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Device Architecture INL – Integral Non-Linearity INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the ...
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Figure 2-90 • Offset Error Resolution ADC resolution is the number of bits used to represent an analog input signal. To more accurately replicate the analog signal, resolution needs to be increased. Sampling Rate Sampling rate or sample ...
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Device Architecture TUE – Total Unadjusted Error TUE is a comprehensive specification that includes linearity errors, gain error, and offset error the worst-case deviation from the ideal device performance. TUE is a static specification Figure 2-91 • Total ...
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Typical Performance Characteristics Temperature Errror vs. Die Temperature 3.5 3 2.5 2 1.5 1 0.5 0 –40 Figure 2-92 • Temperature Error Temperature Error vs. Interconnect Capacitance 500 Figure 2-93 ...
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Device Architecture Figure 2-94 • Temperature Reading Noise When Averaging is Used Temperature Reading Noise RMS vs. Averaging 1 10 100 Number of Averages R e visio n 1 1000 ...
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Analog System Characteristics Table 2-46 • Analog Channel Specifications Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Voltage Monitor Using Analog Pads AV, AC and AT (using prescaler) Input Voltage (Prescaler) Refer ...
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Device Architecture Table 2-46 • Analog Channel Specifications (continued) Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Temperature Monitor Using Analog Pad AT External Resolution Temperature Monitor (external diode 2N3904, 5 Offset ...
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Table 2-46 • Analog Channel Specifications (continued) Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Digital Input using Analog Pads AV, AC and AT 2,3 V Input Voltage IND V Hysteresis HYSDIN ...
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Device Architecture Table 2-47 • ADC Characteristics in Direct Input Mode Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Direct Input using Analog Pad AV, AC Input Voltage (Direct Input) ...
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Table 2-47 • ADC Characteristics in Direct Input Mode (continued) Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Dynamic Performance SNR Signal-to-Noise Ratio SINAD Signal-to-Noise Distortion THD Total Harmonic Distortion ENOB Effective ...
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Device Architecture Table 2-48 • Uncalibrated Analog Channel Accuracy* Worst-Case Industrial Conditions, T Total Channel Error (LSB) Analog Prescaler Neg. Pad Range (V) Max. Med. Positive Range AV –22 –2 8 –40 –5 4 –45 –9 2 –70 ...
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Table 2-49 • Calibrated Analog Channel Accuracy Worst-Case Industrial Conditions, T Analog Pad Prescaler Range (V) Positive Range AV Negative Range AV Notes: 1. Channel ...
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Device Architecture Table 2-50 • Analog Channel Accuracy: Monitoring Standard Positive Voltages Typical Conditions, T Calibrated Typical Error per Positive Prescaler Setting Input Voltage 16 V ( (AT) (AV/AC ...
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Min. Output Voltage = (Min. Negative output offset) + (Input Voltage x Min. Gain) = (–136 mV 0.98) = 4.764 V Calculating Accuracy for a Calibrated Analog Channel Formula For a given prescaler range ...
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Device Architecture Analog Configuration MUX The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter. Actel Libero IDE will generate IP that will load and configure the Analog Block via the ACM. However, users ...
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Table 2-51 • ACM Address Decode Table for Analog Quad (continued) ACMADDR [7:0] in Decimal Note: ACMADDR bytes pertain to the Analog Quads; bytes ...
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Device Architecture Timing Characteristics Table 2-52 • Analog Configuration Multiplexer (ACM) Timing Commercial Temperature Range Conditions: T Parameter t Clock-to-Q of the ACM CLKQACM t Data Setup time for the ACM SUDACM t Data Hold time for the ACM HDACM ...
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Analog Quad ACM Description Table 2-53 maps out the ACM space associated with configuration of the Analog Quads within the Analog Block. Table 2-53 each byte. Subsequent tables will explain each bit setting and how it corresponds to a particular ...
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Device Architecture Table 2-54 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note that the AT pin has a reduced number of available prescaler values. Table 2-54 • Prescaler Control Truth Table—AV ...
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Table 2-58 details the settings available to either power down or enable the prescaler associated with the analog inputs AV, AC, and AT. Table 2-58 • Prescaler Op Amp Power-Down Truth Table— 0 1), and ...
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Device Architecture User I/Os Introduction Fusion devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) through a bank-selectable voltage. page 2-137 show the voltages and the compatible I/O ...
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CCC VREF signal scope is between 8 and 18 I/Os. Figure 2-97 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500) Table 2-64 • I/O Standards Supported by Bank Type I/O Bank Single-Ended I/O Standards ...
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Device Architecture Table 2-65 • I/O Bank Support by Device I/O Bank AFS090 Standard I/O Advanced I Pro I/O Analog Quad Note East side of the device W = West side of the device N = ...
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Table 2-68 • Fusion Standard and Advanced I/O Features 3.3 V – 0.80 V 1.00 V 1.50 V 2.5 V – 0.80 V 1.00 V 1.25 V 1.8 V – 1.5 V – 0.75 V Note: White box: Allowable I/O ...
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Device Architecture Features Supported on Pro I/Os Table 2-69 lists all features supported by transmitter/receiver for single-ended and differential I/Os. Table 2-69 • Fusion Pro I/O Features Feature Single-ended and voltage- referenced transmitter features Single-ended receiver features Voltage-referenced differential receiver ...
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Table 2-70 • Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os; All I/O Bank Types (maximum drive strength and high slew selected) Specification LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V PCI PCI-X HSTL-I HSTL-II ...
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Device Architecture I/O Registers Each I/O module contains several input, output, and enable registers. Refer to simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in registers to implement ...
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Double Data Rate (DDR) Support Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, ...
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Device Architecture Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-100 • DDR Output Support in Fusion Devices FF1 FF2 B C DDR_OUT R e visio n 1 ...
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Hot-Swap Support Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-71. ...
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Device Architecture For Fusion devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to Fusion I/Os need to have 10 kΩ (or lower) output drive resistance at hot insertion, and 1 kΩ (or lower) output drive resistance ...
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Electrostatic Discharge (ESD) Protection Fusion devices are tested per JEDEC Standard JESD22-A114-B. Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage ...
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Device Architecture 5 V Input Tolerance I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2 and LVCMOS 2.5 V configurations are used (see recommended solutions (see setups) to achieve ...
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Temporary overshoots are allowed according to Off-Chip 5.5 V Rext1 Figure 2-101 • Solution 1 Solution 2 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page 3-4. ...
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Device Architecture Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal ...
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Table 2-74 • Comparison Table for 5 V–Compliant Receiver Scheme Schem e Board Components 1 Two resistors 2 Resistor and Zener 3 Bus switch 2 4 Minimum resistor value Ω 70°C J ...
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Device Architecture 5 V Output Tolerance Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers also critical that there be NO external I/O pull-up resistor to ...
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Selectable Skew between Output Buffer Enable/Disable Time The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time. Output Enable ENABLE (IN) (from FPGA core) Skew Circuit Figure 2-105 • Block Diagram of ...
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Device Architecture At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent ...
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EN (b1) EN (b2) ENABLE (t1) Transmitter 1: OFF ENABLE (t2) Transmitter 2: ON Result: No Bus Contention Figure 2-110 • Timing Diagram (with skew circuit selected) Weak Pull-Up and Weak Pull-Down Resistors Fusion devices support optional weak pull-up and ...
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Device Architecture Refer to Table 2-75, Table 2-78 on page 2-155 page 2-157 lists the voltages for the supported I/O standards. Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V ...
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Table 2-78 • Fusion Pro I/O Default Attributes SLEW I/O Standards (output only) LVTTL/LVCMO Refer to the following S 3.3 V tables for more information: LVCMOS 2.5 V Table 2-75 on page 2-154 LVCMOS Table 2-76 on page 2-154 2.5/5.0 ...
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Device Architecture Table 2-79 • Advanced I/O Default Attributes I/O Standards SLEW (output only) LVTTL/LVCMOS 3.3 V Refer to the following tables for more LVCMOS 2.5 V information: LVCMOS 2.5/5.0 V Table 2-75 on page 2-154 Table 2-76 on page ...
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Table 2-80 • Fusion Pro I/O Supported Standards and Corresponding VREF and VTT Voltages Input/Output Supply I/O Standard Voltage (V LVTTL/LVCMOS 3.3 V 3.30 V LVCMOS 2.5 V 2.50 V LVCMOS 2 5.0 V 2.50 V Input LVCMOS ...
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Device Architecture I/O Software Support In the Fusion development software, default settings have been defined for the various I/O standards supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are ...
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Table 2-82 • Fusion Pro I/O Attributes vs. I/O Standard Applications I/O Standards ✓ LVTTL/LVCMOS 3.3 V ✓ LVCMOS 2.5 V ✓ LVCMOS 2.5/5.0 V ✓ LVCMOS 1.8 V ✓ LVCMOS 1.5 V PCI (3.3 V) ✓ PCI-X (3.3 V) ...
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Device Architecture User I/O Naming Convention Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to show the details of the I/O identifies to which I/O bank it belongs, as well as ...
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CCC Bank 0 "A" Bank 4 CCC/PLL "F" Bank 4 CCC "E" Figure 2-112 • Naming Conventions of Fusion Devices with Four I/O Banks Actel Fusion Family of Mixed Signal FPGAs Pro I/O Bank CCC Bank 1 "B" Bank 2 ...
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Device Architecture User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D (Pro IO Banks 0.24 ns ICLKQ t = 0.26 ns Input LVTTL/LVCMOS ISUD 3.3 V (Pro IO banks 0.90 ...
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PY t PYS PAD t = MAX MAX(t PYs t = MAX(t DIN VIH V trip PAD 50% Y GND t PY (R) t PYS (R) 50% DIN t GND DOUT (R) Figure 2-114 • ...
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Device Architecture D From Array Figure 2-115 • Output Buffer Model and Delays (example DOUT D Q DOUT CLK t = MAX(t DP I/O Interface t DOUT t t DOUT DOUT (R) VCC (F) 50% 50% ...
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EOUT D Q CLK DOUT CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip VOL D 50% 50 EOUT (R) VCC 50% EOUT t ZLS PAD ...
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Device Architecture Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to ...
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Table 2-85 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to Standard I/Os Drive Slew Min. I/O Standard Strength Rate 3.3 V LVTTL / 8 mA High –0.3 3.3 V ...
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Device Architecture Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-87 • Summary of AC Measuring Points Applicable to All I/O Bank Types Input Reference Voltage Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS ...
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Table 2-89 • Summary of I/O Timing Characteristics – Software Default Settings Commercial Temperature Range Conditions: T Worst-Case VCCI = I/O Standard Dependent Applicable to Pro I/Os I/O Standard 3.3 V LVTTL High 35 – 3.3 V LVCMOS ...
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Device Architecture Table 2-90 • Summary of I/O Timing Characteristics – Software Default Settings Commercial Temperature Range Conditions: T Worst-Case VCCI = I/O Standard Dependent Applicable to Advanced I/Os I/O Standard 3.3 V LVTTL High 35 pF 3.3 ...
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Detailed I/O DC Characteristics Table 2-92 • Input Capacitance Symbol Definition C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-93 • I/O Output Buffer Maximum Resistances Standard Applicable to Pro I/O Banks 3.3 V LVTTL ...
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Device Architecture Table 2-93 • I/O Output Buffer Maximum Resistances Standard HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V ...
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Table 2-93 • I/O Output Buffer Maximum Resistances Standard Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. These maximum values are provided for informational reasons ...
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Device Architecture Table 2-95 • I/O Short Currents I OSH Applicable to Pro I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Applicable to Advanced I/O Banks 3.3 V LVTTL / ...
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Table 2-95 • I/O Short Currents I /I OSH 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 ...
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Device Architecture Table 2-96 • Short Current Event Duration before Failure Temperature –40°C 0°C 25°C 70°C 85°C 100°C Table 2-97 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers Input Buffer Configuration 3.3 V LVTTL/LVCMOS/PCI/PCI-X ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as ...
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Device Architecture Table 2-100 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) 0 Note: *Measuring point = V . See trip Timing Characteristics Table 2-101 • 3.3 V LVTTL / 3.3 V LVCMOS Low ...
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Table 2-102 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial Temperature Range Conditions: T Worst-Case V = 3.0 V CCI Applicable to Pro I/Os Drive Speed Strength Grade DOUT DP DIN 4 mA Std. ...
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Device Architecture Table 2-103 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.66 ...
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Table 2-104 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.66 7.66 –1 ...
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Device Architecture Table 2-106 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 3.0 V Applicable to Standard I/Os Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 –1 0.56 ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-107 • Minimum and Maximum ...
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Device Architecture Timing Characteristics Table 2-109 • 2.5 V LVCMOS Low Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Speed Strength Grade t t DOUT Std. 0.60 12.00 0.04 ...