M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 13

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Clock Resources
PLLs and Clock Conditioning Circuits (CCCs)
Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of the
Fusion family contains six CCCs. In the two larger family members, two of these CCCs also include a
PLL; the smaller devices support one PLL.
The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with
dedicated CCC block connections.
The CCC block has the following key features:
Additional CCC specifications:
Global Clocking
Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there are on-chip oscillators as well as a comprehensive global clock
distribution network.
The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known clock
source to the flash memory read and write control. It can also be used as a source for the PLLs.
The crystal oscillator supports the following operating modes:
Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant global
networks. The VersaNets can be driven by the CCC or directly accessed from the core via MUXes. The
VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
Digital I/Os with Advanced I/O Standards
The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). Fusion FPGAs support many different digital I/O standards, both single-ended
and differential.
The I/Os are organized into banks, with four or five banks per device. The configuration of these banks
determines the I/O standards supported. The banks along the east and west sides of the device support
the full range of I/O standards (single-ended and differential). The south bank supports the Analog Quads
(analog I/O). In the family's two smaller devices, the north bank supports multiple single-ended digital I/O
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Wide input frequency range (f
Output frequency range (f
Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns
Clock skew minimization (PLL)
Clock frequency synthesis (PLL)
On-chip analog clocking resources usable as inputs:
– 100 MHz on-chip RC oscillator
– Crystal oscillator
Internal phase shift = 0°, 90°, 180°, and 270°
Output duty cycle = 50% ± 1.5%
Low output jitter. Samples of peak-to-peak period jitter when a single global network is used:
– 70 ps at 350 MHz
– 90 ps at 100 MHz
– 180 ps at 24 MHz
– Worst case < 2.5% × clock period
Maximum acquisition time = 150 µs
Low power consumption of 5 mW
Crystal (32.768 KHz to 20 MHz)
Ceramic (500 KHz to 8 MHz)
RC (32.768 KHz to 4 MHz)
OUT_CCC
IN_CCC
) = 0.75 MHz to 350 MHz
) = 1.5 MHz to 350 MHz
R e v i s i o n 1
Actel Fusion Family of Mixed Signal FPGAs
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