M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 199

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Table 2-107 • Minimum and Maximum DC Input and Output Levels
Figure 2-118 • AC Loading
Table 2-108 • AC Waveforms, Measuring Points, and Capacitive Loads
2.5 V
LVCMOS
Drive
Strength
Applicable to Pro I/O Banks
4 mA
8 mA
12 mA
16 mA
24 mA
Applicable to Advanced I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Applicable to Standard I/O Banks
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
Note:
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
Data Path
Test Point
VIL
Input High (V)
Max.
trip
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
V
. See
2.5
35 pF
Table 2-87 on page 2-168
Min.
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
V
VIH
Enable Path
Max.
Test Point
3.6
3.6
3.6
3.6
3.6
2.7
2.7
2.7
2.7
2.7
2.7
2.7
3.6
3.6
3.6
3.6
V
Measuring Point* (V)
R = 1 k
R e v i s i o n 1
Max.
VOL
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
V
1.2
for a complete table of trip points.
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
VOH
Min.
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
V
HZ
mA mA
I
12
16
24
12
16
24
Actel Fusion Family of Mixed Signal FPGAs
OL
ZH
4
8
2
4
6
8
2
4
6
8
/ t
VREF (typ.) (V)
/ t
LZ
HZ
LZ
ZHS
I
12
16
24
12
16
24
OH
4
8
2
4
6
8
2
4
6
8
/ t
/ t
ZL
ZH
/ t
–
ZL
/ t
/ t
Max.
mA
I
124
124
OSL
18
37
74
87
18
18
37
37
74
87
18
18
37
37
ZLS
/ t
ZHS
ZLS
3
Max.
mA
I
169
169
OSH
16
32
65
83
16
16
32
32
65
83
16
16
32
32
C
3
LOAD
µA
35
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IL
1
(pF)
4
µA
2- 183
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IH
2
4