M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 238

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Device Architecture
Figure 2-141 • Input DDR Timing Diagram
Table 2-177 • Input DDR Propagation Delays
2- 22 2
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
CLK
Data
CLR
Out_QF
Out_QR
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
3-9.
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
Timing Characteristics
t
t
1
DDRICLR2Q2
DDRICLR2Q1
t
DDRIREMCLR
2
3
Description
t
DDRICLKQ1
4
2
R e visio n 1
3
J
5
= 70°C, Worst-Case VCC = 1.425 V
t
DDRICLKQ2
t
DDRISUD
6
4
1,404
0.39
0.57
0.22
0.22
0.36
0.32
0.27
0.28
0.00
0.46
0.00
5
–2
7
1,048
0.44
0.31
0.32
0.00
0.65
0.25
0.25
0.41
0.37
0.53
0.00
–1
t
DDRIHD
t
DDRIRECCLR
6
8
7
1,232
0.52
0.37
0.38
0.00
0.76
0.62
0.00
0.30
0.30
0.48
0.43
Std.
Table 3-7 on
Units
9
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns