M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 167

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Figure 2-105 • Block Diagram of Output Enable Path
Figure 2-106 • Timing Diagram (option1: bypasses skew circuit)
Figure 2-107 • Timing Diagram (option 2: enables skew circuit)
(from FPGA core)
ENABLE (OUT)
Output Enable
ENABLE (OUT)
ENABLE (IN)
ENABLE (IN)
ENABLE (IN)
Less than
0.1 ns
(typical)
1.2 ns
Skew Circuit
R e v i s i o n 1
Skew Select
MUX
Less than
0.1 ns
Less than
0.1 ns
Actel Fusion Family of Mixed Signal FPGAs
ENABLE (OUT)
I/O Output
Buffers
2- 151