M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 176

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Device Architecture
2- 16 0
I/O Nomenclature
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
G
m
n
u
x
w
B
y
V
z
= Global
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C
= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1,
= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise
= P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support single-
= D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded
= Bank
= Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise
= Reference voltage
= Minibank number
(east middle), D (southeast corner), E (southwest corner), and F (west middle).
or C2.
direction.
ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict
the I/O differential pair from being selected as an LVPECL pair.
out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are
bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.
For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal
adjacency does not meet the requirements for a true differential pair.
direction.
User I/O Naming Convention
Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to
show the details of the I/O
identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os.
Figure 2-111 • Naming Conventions of Fusion Devices with Three Digital I/O Banks
Figure 2-22 on page 2-27
= Gmn/IOuxwByVz
CCC/PLL
Bank 3
Bank 3
CCC
"A"
CCC
"E"
"F"
shows the three input pins per clock source MUX at CCC location m.
(Figure 2-111 on page 2-160
Standard I/O Bank
Analog Quads
R e visio n 1
Bank 2 (analog)
AFS090
AFS250
Bank 0
and
Figure 2-112 on page
Bank 1
Bank 1
CCC
"B"
CCC
"C"
CCC
"D"
2-161). The name