MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 100

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Table 42: WRITE Using Concurrent Auto Precharge
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
WRITE with auto precharge
From Command
(Bank n)
±
the WRITE diagrams show the nominal case, and where the two extreme cases (
[MIN] and
(page 101) shows the nominal case and the extremes of
pletion of a burst, assuming no other commands have been initiated, the DQ will re-
main High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 56 (page 102) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 57 (page 102). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 42.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-
charge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 58
(page 103).
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE,
cycles required to meet
WRITE burst may be followed by a subsequent PRECHARGE command.
met, as shown in Figure 60 (page 105).
of the data mask condition.
t
DQSS.
WRITE or WRITE with auto precharge
READ or READ with auto precharge
t
DQSS is specified with a relatively wide range (25% of one clock cycle). All of
t
PRECHARGE or ACTIVATE
WTR should be met, as shown in Figure 59 (page 104). The number of clock
t
DQSS [MAX]) might not be intuitive, they have also been included. Figure 55
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To Command
(Bank m)
t
WTR is either 2 or
100
512Mb: x8, x16 Automotive DDR2 SDRAM
t
WR starts at the end of the data burst, regardless
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WTR/
(with Concurrent Auto Precharge)
t
CK, whichever is greater. Data for any
(CL - 1) + (BL/2) +
Minimum Delay
t
DQSS for BL = 4. Upon com-
(BL/2)
1
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t
WTR
t
WR must be
t
WRITE
DQSS
Units
t
t
t
CK
CK
CK