MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 125

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

MRS Command to ODT Update Delay
Figure 79: Timing for MRS Command to ODT Update Delay
Figure 80: ODT Timing for Active or Fast-Exit Power-Down Mode
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command.
R
Command
Command
TT
Address
Internal
1. The LM command is directed to the mode register, which updates the information in
2. To prevent any impedance glitch on the channel, the following conditions must be met:
setting
ODT 2
ODT
CK#
CKE
R
CK#
CK
CK
EMR (A6, A2), that is, R
t
tire duration of the
TT
AOFD must be met before issuing the LM command; ODT must remain LOW for the en-
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Valid
Valid
T0
T0
Old setting
t AOFD
t CK
EMRS 1
Ta0
Valid
Valid
T1
t
t CH
0ns
MOD window until
TT
125
(nominal).
t CL
t AON (MIN)
512Mb: x8, x16 Automotive DDR2 SDRAM
t AOND
NOP
Ta1
Valid
Valid
t AON (MAX)
T2
t MOD
t
MOD (MAX) updates the R
Undefined
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NOP
Ta2
Valid
Valid
T3
t AOFD
t
MOD is met.
R
TT
Unknown
NOP
Ta3
Valid
Valid
T4
t IS
t AOF (MIN)
R
2
Ta4
NOP
Valid
Valid
TT
T5
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t AOF (MAX)
On
New setting
Indicates a break in
time scale
TT
setting.
NOP
Ta5
Valid
Valid
Don’t Care
T6
ODT Timing