MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 119
![no-image](/images/no-image-200.jpg)
MT47H32M16HR-25E AIT:G
Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
1.MT47H64M8CF-25E_ITG.pdf
(129 pages)
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Figure 74: PRECHARGE Command-to-Power-Down Entry
Figure 75: LOAD MODE Command-to-Power-Down Entry
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
Note:
Command
Command
Address
Address
1. The earliest precharge power-down entry may occur is at T2, which is 1 ×
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and
3. The earliest precharge power-down entry is at T3, which is after
CK#
CKE
CK#
A10
CKE
CK
PRECHARGE command. Precharge power-down entry occurs prior to
isfied.
CK
Valid
Micron Confidential and Proprietary
T0
Valid
T0
t RP 2
Valid 1
LM
T1
Single bank
Valid
All banks
119
PRE
T1
vs
512Mb: x8, x16 Automotive DDR2 SDRAM
1 x
t MRD
t
CK
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Power-down 1
T2
entry
NOP
T2
t
Power-down 3
RP met prior to issuing LM command.
entry
NOP
T3
t
CKE (MIN)
T3
Power-Down Mode
2010 Micron Technology, Inc. All rights reserved.
t CKE (MIN)
Don’t Care
t
MRD is satisfied.
T4
t
RP (MIN) being sat-
Don’t Care
t
CK after the
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