MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 111

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

SELF REFRESH
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
fresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-
ing any other command.
Micron Confidential and Proprietary
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XSNR. A simple algorithm for meeting both refresh and DLL require-
111
512Mb: x8, x16 Automotive DDR2 SDRAM
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CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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CK specifications at least 1 ×
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CKE [MIN] has been satisfied
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CK after entering self re-
SELF REFRESH
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CK