MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 120

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MT47H32M16HR-25E AIT:G

Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
Precharge Power-Down Clock Frequency Change
Figure 76: Input Clock Frequency Change During Precharge Power-Down Mode
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
DQS, DQS#
Command
Address
ODT
CK#
CKE
DM
DQ
CK
High-Z
High-Z
Valid 4
Valid
T0
t CH
power-down mode
t CK
Enter precharge
Notes:
t CL
Previous clock frequency
NOP
T1
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating fre-
quencies specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels. When the input clock frequency is
changed, new stable clocks must be provided to the device before precharge power-
down may be exited, and DLL must be reset via MR after precharge power-down exit.
Depending on the new clock frequency, additional LM commands might be required to
adjust the CL, WR, AL, and so forth. Depending on the new clock frequency, an addi-
tional LM command might be required to appropriately set the WR MR9, MR10, MR11.
During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock
time, the DRAM is ready to operate with a new clock frequency.
1. A minimum of 2 ×
2. When the new clock frequency has changed and is stable, a minimum of 1 ×
2 x t CK (MIN) 1
ing clock frequencies.
quired prior to exiting precharge power-down.
T2
t CKE (MIN) 3
Micron Confidential and Proprietary
T3
Frequency
Precharge Power-Down Clock Frequency Change
change
t
CK is required after entering precharge power-down prior to chang-
Ta0
120
1 x t CK (MIN) 2
512Mb: x8, x16 Automotive DDR2 SDRAM
t CH
power-down mode
t CK
Exit precharge
t CL
NOP
Ta1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
New clock frequency
NOP
t XP
Ta2
t CKE (MIN) 3
DLL RESET
Ta3
LM
Indicates a break in
time scale
‹ 2010 Micron Technology, Inc. All rights reserved.
200 x t CK
NOP
Ta4
t
Don’t Care
Valid
CK is re-
Valid
Tb0

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