MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 75

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Write Recovery
Power-Down Mode
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 33 (page 73).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 62 (page 107).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 33. PD mode
enables the user to determine the active power-down mode, which determines per-
formance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-
abled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in the DDR2 I
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
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t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
75
512Mb: x8, x16 Automotive DDR2 SDRAM
t
CK (ns). Reserved states should not be used as an un-
DD
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Specifications and Conditions table.
DD3P
Mode Register (MR)
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normal and I
t
WR (in
DD3P
low-