MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 26

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Table 10: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Parameter/Condition
Burst refresh current:
mand at every
between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE
er control and address bus inputs are floating; Data bus
inputs are floating
Operating bank interleave read
current: All bank interleaving reads, I
CL = CL (I
t
HIGH, CS# is HIGH between valid commands; Address bus
inputs are stable during deselects; Data bus inputs are
switching; See I
RC =
t
RC (I
DD
DD
), AL =
),
t
t
DD7
RFC (I
RRD =
t
DD
RCD (I
Conditions (page 24) for details
DD
Notes:
t
Specifications and Conditions (Continued)
RRD (I
) interval; CKE is HIGH, CS# is HIGH
t
CK =
DD
) - 1 ×
DD
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
CK (I
),
t
UDQS#. I
devices when operated outside of the range 0°C
t
RCD =
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
When
T
CK (I
DD
DD
DD1
DD
C
C
DD
specifications are tested after the device is properly initialized. 0°C
parameters are specified with ODT disabled.
, I
); REFRESH com-
OUT
= 1.8V ±0.1V, V
DD
0°C
85°C
DD4R
t
Micron Confidential and Proprietary
RCD (I
);
= 0mA; BL = 4,
DD
t
, and I
CK =
I
ed by 2%; and I
I
ed by 2%; I
30%; and I
T
values must be met with all combinations of EMR bits 10 and 11.
DD2P
DD0
C
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
DD
< 85°C and the 2X refresh option is still enabled)
IN
IN
0.2V; Oth-
, I
DD
t
DD
); CKE is
CK (I
DD7
and I
DD1
V
V
values must be derated (I
conditions:
DDQ
IL(AC)max
IH(AC)min
require A12 in EMR to be enabled during testing.
, I
DD
DD3P(SLOW)
DD2N
DD6
DD2P
),
REF
= 1.8V ±0.1V, V
must be derated by 80% (I
26
, I
Symbol
= V
DD6
512Mb: x8, x16 Automotive DDR2 SDRAM
must be derated by 20%; I
DD2Q
Electrical Specifications – I
I
I
I
I
DD6L
DD5
DD6
DD7
DDQ
and I
must be derated by 4%; I
, I
/2
DD3N
DD7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Configuration
DDL
, I
must be derated by 7%
DD3P(FAST)
= 1.8V ±0.1V, V
x8, x16
DD
x16
x16
x8
x8
limits increase) on IT-option and AT-option
, I
T
DD4R
C
DD6
DD3P(SLOW)
85°C:
, I
will increase by this amount if
DD4R
DD4W
REF
-25E/
100
150
215
-25
95
7
3
= V
‹ 2010 Micron Technology, Inc. All rights reserved.
and I
, and I
must be derated by
DDQ
DD5W
/2.
DD
DD5W
-3E/
140
200
90
90
Parameters
-3
must be derat-
7
3
T
must be derat-
C
+85°C.
Units
mA
mA
mA