MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 131
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Table 156. Output Compare 3 Mask Register (OC3M)
Table 158. Output Compare 3 Data Register (OC3D)
Note:
Note:
Functional Description and Application Information
A write to this register with the corresponding (FOC 3:0) data bit(s) set causes the action programmed for output compare on
channel “n” to occur immediately.The action taken is the same as if a successful comparison had just taken place with the TCn
register except the interrupt flag does not get set.
4.18.3.3.3
Setting the OC3Mn (n ranges from 0 to 2) will set the corresponding port to be an output port when the corresponding TIOSn (n
ranges from 0 to 2) bit is set to be an output compare.
4.18.3.3.4
Freescale Semiconductor
Offset
117.
Offset
118.
Table 157. OC3M - Register Field Descriptions
Reset
Reset
W
W
R
R
OC3M[3-0]
(117)
(118)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
3-0
0xC2
0xC3
7
0
0
7
0
0
Output Compare 3 Mask “n” Channel bit
0 - Does not set the corresponding port to be an output port
1 - Sets the corresponding port to be an output port when this corresponding TIOS bit is set to be an output compare
A successful channel 3 output compare overrides any channel 2:0 compares. If forced
output compare on any channel occurs at the same time as the successful output compare
then forced output compare action will take precedence and interrupt flag will not get set.
Output Compare 3 Mask Register (OC3M)
A successful channel 3 output compare overrides any channel 2:0 compares. For each
OC3M bit that is set, the output compare action reflects the corresponding OC3D bit
Output Compare 3 Data Register (OC3D)
A channel 3 output compare will cause bits in the output compare 3 data register to transfer
to the timer port data register if the corresponding output compare 3 mask register bits are
set.
6
0
0
6
0
0
0
0
0
0
5
5
NOTE
NOTE
NOTE
0
0
0
0
4
4
Description
OC3M3
OC3D3
0
0
3
3
Basic Timer Module - TIM (TIM16B4C)
OC3M2
OC3D2
0
0
2
2
OC3M1
OC3D1
1
0
1
0
Access: User read/write
Access: User read/write
MM912F634
OC3M0
OC3D0
0
0
0
0
131
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