MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 225
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Functional Description and Application Information
4.31.3.2.7.4
Table 287. Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly to a channel. Should a
match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the
module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These
flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other
flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag.
4.31.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map.
Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask
registers and a control register). Comparator B consists of four register bytes (three address bus compare registers and a control
register). Comparator C consists of four register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g.
Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs
from those of comparators A and C.
Table 288. Comparator Register Layout
Freescale Semiconductor
Address: 0x0027
Reset
0x002A
0x002B
0x002C
0x002D
0x002E
W
0x0028
0x0029
0x002F
R
0
0
7
Debug Match Flag Register (DBGMFR)
Comparator Register Descriptions
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
0
0
6
CONTROL
5
0
0
0
0
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
0
0
3
MC2
S12S Debug (S12SDBGV1) Module
0
2
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparator A only
Comparator A only
Comparator A only
Comparator A only
MC1
1
0
MM912F634
MC0
0
0
225
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