MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 79
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Note:
Note:
Functional Description and Application Information
4.9.1
4.9.1.1
Table 91. Watchdog Register (WDR)
4.9.1.2
Table 93. Watchdog Service Register (WDSR)
Freescale Semiconductor
Offset
Offset
76.
77.
Reset
Table 92. WDR - Register Field Descriptions
Reset
Table 94. WDSR - Register Field Descriptions
W
W
R
R
7 - WDOFF
WDTO[2:0]
6 - WDWO
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(76)
(77)
WDSR
Field
Field
2-0
7-0
0x10
0x11
WDOFF
Register Definition
0
0
7
7
Watchdog Register (WDR)
Watchdog Service Register (WDSR)
watchdog Off - Indicating the Watchdog module is being disabled externally.
Watchdog Window Open - Indicating the Watchdog Window is currently open for counter reset.
Watchdog Timeout Configuration - configuring the Watchdog timeout duration t
000 - 10 ms
001 - 20 ms
010 - 40 ms
011 - 80 ms
100 - 160 ms
101 - 320 ms
110 - 640 ms
111 - 1280 ms
Watchdog Service Register - Writing this register with the correct value (0xAA alternating 0x55) while the window is open
will reset the watchdog counter. Writing the register while the watchdog is disabled will have no effect.
WDWO
0
1
6
6
5
0
0
5
0
4
0
0
4
1
WDSR
Description
Description
0
0
0
3
3
WDTO
0
1
2
2
.
WDTO
0
0
1
1
Access: User read/write
Access: User read/write
Window Watchdog
MM912F634
0
1
0
0
79
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