MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 215
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Functional Description and Application Information
4.31.1.4
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active
BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Table 258. Mode Dependent Restriction Summary
4.31.1.5
Freescale Semiconductor
Enable
BDM
•
•
x
0
0
1
1
TAGHITS
SECURE
CPU BUS
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
READ TRACE DATA (DBG READ DATA BUS)
definition.
Modes of Operation
Active
Block Diagram
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
COMPARATOR A
COMPARATOR C
COMPARATOR B
Figure 69. Debug Module Block Diagram
Matches Enabled
Comparator
Yes
Yes
Yes
No
MATCH1
MATCH0
MATCH2
Active BDM not possible when not enabled
Breakpoints
Possible
Only SWI
Section 4.31.4.5.3, “Normal
Yes
Yes
CONTROL
No
MATCH
LOGIC
TAG &
TRANSITION
STATE
S12S Debug (S12SDBGV1) Module
BREAKPOINT REQUESTS
Possible
Tagging
Yes
Yes
Yes
No
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
Mode") for change of flow
STATE
TRACE
CONTROL
TRIGGER
Possible
Tracing
MM912F634
Yes
Yes
No
No
215
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