MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 303
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Table 388. D2DI Control Register 0 (D2DCTL0)
Table 387. D2DI Register Summary
Functional Description and Application Information
A summary of the registers associated with the D2DI block is shown in
are given in the subsections that follow.
4.37.3.2
4.37.3.2.1
This register is used to enable and configure the interface width, the wait behavior and the frequency of the interface clock.
Table 389. D2DCTL0 Register Field Descriptions
Freescale Semiconductor
Address
0x00DA
0x00DB
0x00DC
0x00DD
0x00DE
0x00D8
0x00D9
0x00DF
Reset
0x00D8
W
D2DCW
R
D2DEN
Field
7
6
D2DDATALO
D2DDATAHI
D2DADRLO
D2DADRHI
D2DSTAT0
D2DSTAT1
D2DEN
D2DCTL0
D2DCTL1
Register
D2DI Enable — Enables the D2DI module. This bit is write-once in normal mode and can always be written in special modes.
0 D2DI initiator is disabled. No lines are not used, the pins have their GPIO (secondary) function.
1 D2DI initiator is enabled. After setting D2DEN = 1 the D2DDAT[7:0] (or [3:0], see D2DCW) lines are driven low with the IDLE
D2D Connection Width — Sets the number of data lines used by the interface. This bit is write-once in normal modes and can
always be written in special modes.
0 Lines D2DDAT[3:0] are used for four line data transfer. D2DDAT[7:4] are unused.
1 All eight interface lines D2DDAT[7:0] are used for data transfer.
Name
Register Definition
7
0
command; the D2DCLK is driven by the divided bus clock.
D2DI Control Register 0 (D2DCTL0)
W
W
W
W
W
W
R
R
R
R
R
R
D2DCW
6
0
D2DEN
ERRIF
D2DIE
D2DIF
RWB
Bit 7
D2DSWAI
ACKERF
D2DBSY
D2DCW
0
SZ8
5
6
0
D2DSWAI
CNCLF
5
0
0
0
0
0
4
Description
TIMEF
NBLK
Figure
4
0
0
0
DATA[15:8]
DATA[7:0]
ADR[7:0]
0
0
3
48. Detailed descriptions of the registers and bits
TERRF
3
0
0
0
0
0
2
PARF
TIMEOUT[3:0]
2
0
0
0
Die-to-Die Initiator (D2DIV1)
1
0
D2DCLKDIV[1:0]
Access: User read/write
PAR1
D2DCLKDIV[1:0]
1
0
0
MM912F634
PAR0
Bit 0
0
0
0
0
303
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