MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 330
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Functional Description and Application Information
4.38.4.7
4.38.4.7.1
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled
state. SPI registers remain accessible, but clocks to the core of this module are disabled.
4.38.4.7.2
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.
4.38.4.7.3
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the
SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop
mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with
the master.
The stop mode is not dependent on the SPISWAI bit.
Freescale Semiconductor
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If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU
is in wait mode.
If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode
entry. The transmission and reception resumes when the SPI exits wait mode.
If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK
continues to be driven from the master. This keeps the slave synchronized to the master and the SCK.
If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent
with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will
continue to send the same byte. Else, if the slave is currently sending the last received byte from the master, it will
continue to send each previous master byte).
Low Power Mode Options
SPI in Run Mode
SPI in Wait Mode
Care must be taken when expecting data from a master while the slave is in wait or stop
mode. Even though the shift register will continue to operate, the rest of the SPI is shut down
(i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte
from the shift register will not be copied into the SPIDR register until after the slave SPI has
exited wait or stop mode. In slave mode, a received byte pending in the receive shift register
will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only
if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle
mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
SPI in Stop Mode
NOTE
Serial Peripheral Interface (S12SPIV4)
MM912F634
330
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