ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 12

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
2.2.
In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by
setting the DIGENB bit (R25, bit 0).
0x1A
Power Management 1
Register Address
Stopping the Master Clock
Note: Before DIGENB can be set, the control bits ADCL, ADCR, HPL, HPR, SPKL, and SPKR
must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain
fading to complete. Any failure to follow this procedure may cause pops or, if less than 1mS, may
prevent the DACs and ADCs from re-starting correctly.
Bit
0
Table 3. Power Management Register1 -- Master Clock Disable
DIGENB
Label
Type
RW
Default
12
0
Master clock disable
0 = master clock enabled, 1 = master clock disabled
Description
ACS422X68
V1.6 01/13