ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 70

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
•
The controller may read more than one register within a single read cycle. To read additional registers, the controller
will not generate a stop or start (repeated start) command after sending the acknowledge for the byte of data. Instead
the controller will continue to provide clocks and acknowledge after each byte of received data. The codec will automat-
ically increment the internal register address after each register has had its data successfully read (ACK from host) but
will not increment the register address if the data is not received correctly by the host (nACK from host) or if the bus
cycle is terminated unexpectedly (however the EQ/Filter address will be incremented even if the register address is not
incremented when performing EQ/Filter RAM reads). By automatically incrementing the internal register address after
each byte is read, all the internal registers of the codec may be read in a single read cycle.
Device Address Register
R124 (7Ch)
DEVADR
SCL
SDA
Register Address
S
START
5.9.4.
5.9.5.
DA[6:0]
Set Register Address
Device Address DA[6:0]
The ACS422x68 has device address D2.
Multiple Read Cycle
nW ACK
Device Addressing and Identification
The ACS422x68 has a default slave address of D2. However, it is sometimes necessary to use a dif-
ferent address. The ACS422x68 has a device address register for this purpose. The part itself has
an 8-bit Identification register and an 8-bit revision register that provide device specific information
for software. In addition, an 8-bit programmable subsystem ID register can allow firmware to provide
a descriptive code to higher level software such as an operating system driver or application soft-
ware.
5.9.5.1.
Bit
7:1
0
RA[7:0]
Device Registers
nW
ADDR[7:1]
ACK
ACK
RSVD
Label
Sr
Register Address RA[7:0]
Figure 33. Multiple Read Cycle
Table 75. DEVADRl Register
DA[6:0]
Read Register @ RA[7:0]
Figure 32. Read Cycle
Type
RW
R
R
ACK
1101001 7-bit slave address
Default
70
ACK
RESTART
0
RD[7:0]
Device Address DA[6:0]
Not used - this bit is the R/nW bit in the 2-wire
protocol.
ACK
Read Register
@ RA[7:0] + 1
RD[7:0]
R
ACK
Description
ACK
Register Data RD[7:0]
Read Register
@ RA[7:0] + n
RD[7:0]
nACK
nACK
STOP
P
ACS422X68
V1.6 01/13