ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 17

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
•
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R58 (3Ah)
DACCRAM_WRITE_LO
R59 (3Bh)
DACCRAM_WRITE_MID
R60 (3Ch)
DACCRAM_WRITE_HI
R61 (3Dh)
DACCRAM_READ_LO
R62 (3Eh)
DACCRAM_READ_MID
R63 (3Fh)
DACCRAM_READ_HI
EQ Filter Enable Register
DACCRAM Read Data (0x3D–LO, 0x3E–MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI)
Registers
These two 24-bit registers provide the 24-bit data holding registers used when doing indirect writes/reads to the DAC
Coefficient RAM.
Register Address
R32 (20h)
CONFIG1
Register Address
3.4.2.
EQ Registers
Bit
6:4
2:0
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7
3
DACCRWD[23:16]
DACCRRD[23:16]
DACCRWD[15:8]
DACCRRD[15:8]
DACCRWD[7:0]
EQ2_BE[2:0]
EQ1_BE[2:0]
DACCRRD[7:0]
EQ2_EN
EQ1_EN
Label
Label
Table 10. DACCRAM Read/Write Registers
Table 9. CONFIG1 Register
Type
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R
R
R
Default
17
Default
0
0
0
0
0
0
0
0
0
0
EQ bank 2 enable
0 = second EQ bypassed, 1 = second EQ enabled
EQ2 band enable. When the EQ is enabled the
following EQ stages are executed.
0 - Prescale only
1 - Prescale and Filter Band 0
...
6 - Prescale and Filter Bands 0 to 5
7 - RESERVED
EQ bank 1 enable
0 = first EQ bypassed, 1 = first EQ enabled
EQ1 band enable. When the EQ is enabled the
following EQ stages are executed.
0 - Prescale only
1 - Prescale and Filter Band 0
...
6 - Prescale and Filter Bands 0 to 5
7 - RESERVED
Low byte of a 24-bit data register, contains the values
to be written to the DACCRAM. The address written will
have been specified by the DACCRAM Address fields.
Middle byte of a 24-bit data register, contains the
values to be written to the DACCRAM. The address
written will have been specified by the DACCRAM
Address fields.
High byte of a 24-bit data register, contains the values
to be written to the DACCRAM. The address written will
have been specified by the DACCRAM Address fields.
Low byte of a 24-bit data register, contains the contents
of the most recent DACCRAM address read from the
RAM. The address read will have been specified by the
DACCRAM Address fields.
Middle byte of a 24-bit data register, contains the
contents of the most recent DACCRAM address read
from the RAM. The address read will have been
specified by the DACCRAM Address fields.
High byte of a 24-bit data register, contains the
contents of the most recent DACCRAM address read
from the RAM. The address read will have been
specified by the DACCRAM Address fields.
Description
Description
ACS422X68
V1.6 01/13